RISC-V intentionally contained almost no innovation of any kind. The whole point was to have the most boring, standard RISC design imaginable, without anything clever in it. That's what you want for introducing students to their first RISC architecture, and also as a basis for doing computer architecture or CPU fabrication research: on zero-overhead loops, compressed instruction sets, scalable vector instruction sets, IoT machine learning, indium gallium zinc oxide thin-film transistors printed on kapton, zero-knowledge virtual machines, or whatever.

They specifically wanted to avoid the kinds of "quirks" that vendors like Intel and ARM used to make people subject to their patents.

They did try to avoid what they saw as the blunders of past designs, like not leaving enough opcode space for compressed instructions, making instructions conditional, leaving out byte and halfword memory access instructions, having a flags register, having a complicated page table structure, having register windows, having delay slots, etc. None of that was innovative. The actual design of the compressed instruction set and the vector instruction set were innovative, but that came later.