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A comment on Samsung Demonstrates 3D Stacked FETs with Triple Nanosheet Channels at 42nm. Parent comment

Re:Samsung Demonstrates 3D Stacked FETs with Triple Nanoshee... by saltcured on Tuesday June 23, 2026 @03:10PM (#48649861)
The shorter connections could lead to faster rise times though, right? I.e. less capacitance or inductance interfering with getting the field gate charged up?

And the main loss with switching transistors is in the intermediate switching states where it has less than its "full" resistance.

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Re:Samsung Demonstrates 3D Stacked FETs with Triple Nanoshee... by marcosdumay on Wednesday June 24, 2026 @12:03AM (#48654952)
> The shorter connections could lead to faster rise times though, right?

Not if you replace that length with more capacitors stacked on top of each other.

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Re:Samsung Demonstrates 3D Stacked FETs with Triple Nanoshee... by saltcured on Wednesday June 24, 2026 @11:52AM (#48661748)
Hah, yeah.

I've been naively assuming they are now making high quality vias, so that circuit characteristics would be similar in either vertical or horizontal direction.

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