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Re:Samsung Demonstrates 3D Stacked FETs with Triple Nanoshee... by ben_w on Tuesday June 23, 2026 @01:57PM (#48648729)
I'm not certain (never did hardware), but I thought the transistor switching cost was one of the bigger sources of energy loss, not internal conductor resistance between transistors?
Re:Samsung Demonstrates 3D Stacked FETs with Triple Nanoshee... by saltcured on Tuesday June 23, 2026 @03:10PM (#48649861)
The shorter connections could lead to faster rise times though, right? I.e. less capacitance or inductance interfering with getting the field gate charged up?

And the main loss with switching transistors is in the intermediate switching states where it has less than its "full" resistance.

Re:Samsung Demonstrates 3D Stacked FETs with Triple Nanoshee... by marcosdumay on Wednesday June 24, 2026 @12:03AM (#48654952)
> The shorter connections could lead to faster rise times though, right?

Not if you replace that length with more capacitors stacked on top of each other.

Re:Samsung Demonstrates 3D Stacked FETs with Triple Nanoshee... by saltcured on Wednesday June 24, 2026 @11:52AM (#48661748)
Hah, yeah.

I've been naively assuming they are now making high quality vias, so that circuit characteristics would be similar in either vertical or horizontal direction.

Re:Samsung Demonstrates 3D Stacked FETs with Triple Nanoshee... by deepsun on Tuesday June 23, 2026 @02:02PM (#48648811)
Makes sense, I also doubt that they haven't minimized resistance to minimum already.
Re:Samsung Demonstrates 3D Stacked FETs with Triple Nanoshee... by IshKebab on Tuesday June 23, 2026 @02:12PM (#48648988)
You're correct. Dynamic power consumption depends heavily on frequency, but it's definitely more of a limiting factor than static power consumption which as I understand it (I'm also not an expert) is mainly important for things like low power microcontrollers.