> I know that we've started using uev since then which seems like it would change things.

Are you asking about EUV lithography? That's a manufacturing technique, but this thesis is about modeling the physics of how a transistor operates, not the process of building the transistor.

They are implying that due to smaller features, the transistors change and if these models still hold for those smaller transistors.

Classic hn well akshully.

Well I think both commentators are valid- the effect of shrinking a transistor but keeping the same geometry is probably well captured by this model. Going from a "10 nm" DUV finFET to a "7 nm" EUV finFET, this model probably works quite well whether you're manufacturing using EUV or DUV.

I think the crux of the matter is the transition from 7 nm down to our modern nodes, where the major change was not only going from DUV to EUV, but perhaps more importantly the change from finFET to multi-gate or gate-all-around FET (GAAFET), where this model probably needs significant updates to be still valid.

The is answer the GP was looking for, thank you.

This thesis already covers GAAFETs. What might be problematic is that it's modeling cylindrical GAA structures, when fabs are trying to implement GAA with ribbon/sheet style structures that this model might not be able to handle.

good point, I didn't read closely enough! The geometry of the GAAFET is definitely changes the physical model a lot (among the most important factors probably?)

So did wtallis just invalidate his own admonishment of noosphr's question?

This feels like a hn breakthrough.

This might be changing with the slowdown in node advancements, but I think it's unlikely you are going to get anything truly "state-of-the-art" in publication research. Academia has trailed industry in this kind of transistor level semiconductor physics for years now. The majority of the state-of-the-art models are closely held in your usual suspects (Intel, TSMC, etc), and are likely considered significant trade secrets.

Aren't the fab models usually rough and binned? Which is why companies have modeling departments.

nope. Fab models are extremely accurate for mature nodes (like anything down to 3nm now). They keep updating after qualification runs, but you see they converge within 1-2 years. Even failure modes and probabilities are modelled extremely accurately

This is if you run full electrical circuit simulation. For complex digital chips you can't do that due to insane compute requirements. There comes in modeling and yield estimation wizardry in. But if you want to simulate the hell out of a reasonably small circuit (< 100M nodes), you can do that extremely accurately.

The models themselves belong to the companies that make the software EDA tools for circuit simulation, i.e. Synopsys, Cadence, Siemens (ex Mentor).

While the models used in commercial EDA tools are based on those published by academic research, they may have various secret tweaks.

What belongs to the foundries, e.g. TSMC, Samsung, Intel, UMC, Global Foundries etc., or to the in-house semiconductor plants of certain companies, are the values of the model parameters, which are determined by fabricating and measuring a lot of test devices.

The foundries provide the model parameters to their customers included in the so-called Process Design Kits. For each semiconductor device fabrication process there is a PDK.

In order to design some custom integrated circuit, you need to obtain the PDK and install it in your simulation tools.

Unfortunately, the foundries with up-to-date fabrication processes keep secret their PDKs. Otherwise many people could attempt to design something like a CPU competitive with Intel, because unlike for fabrication, for design all you need is a computer and time.

Attempting to design a CPU using one of the obsolete PDKs that are available publicly, which are at the level used for CPUs like Pentium 4, more than 20 years ago, is futile, because the optimal design choices are very different for such ancient CMOS fabrication processes, in comparison with modern processes, so you would not learn more from that experience than when targeting an FPGA.

Isn't it that models themselves are public (like BSIM) but what you get in a PDK is a macromodel wrapping BSIM with another zillion of fudge factors, or at least binned by device size? That's what I understood by peeking into various PDK models.

Not every fab use BSIM models. Philips (now NXP) use PSP models for their own fabs and implement them as verilog-a code. This is a physics based model instead of fitted model like BSIM.

TSMC has their own C-library on top of BSIM models for FinFETs because BSIM isn't covering what they need. I don't know what will they use for GAA stuff.

State of the art in transistors?

- "Researchers get spiking neural behavior out of a pair of [CMOS] transistors" (2025) https://news.ycombinator.com/item?id=43503644

- Memristors

- Graphene-based transistors

EUV and nanolithography?

SOTA alternatives to EUV for nanolithography include NIL nanoimprint lithography (at 10-14nm at present fwiu), nanoassembly methods like atomic/molecular deposition and optical tweezers, and a new DUV solid-state laser light source at 193nm.