DDR5 uses burst length 16, so think of it as 512 data bits with 64 ECC bits out of 576 total.

Sure, it is, but that doesn't explain how it works. Previous generations made it simple, they did SECDED ECC (or sometimes chipkill) one transfer at a time no matter what the transaction size was. DDR5 EC4 can't do that, so what does it do?

And does EC8 do SECDED one transfer at a time, or does it do something more resilient?

(And sure technically it's up to the memory controller to implement, but are different controllers doing different things with DDR5?)

72-bit DDR5 is nonstandard to begin with and I assume AMD and Intel are using undocumented ECC codes. There might be hints in patents.