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Re:Micron Samples 256 GB DDR5-8800 MCR DIMMs: Modules for Se... by Dylan16807 on Saturday March 23, 2024 @02:37AM (#39797928)
Sure, it is, but that doesn't explain how it works. Previous generations made it simple, they did SECDED ECC (or sometimes chipkill) one transfer at a time no matter what the transaction size was. DDR5 EC4 can't do that, so what does it do?

And does EC8 do SECDED one transfer at a time, or does it do something more resilient?

(And sure technically it's up to the memory controller to implement, but are different controllers doing different things with DDR5?)

Re:Micron Samples 256 GB DDR5-8800 MCR DIMMs: Modules for Se... by wmf on Saturday March 23, 2024 @12:11PM (#39800917)
72-bit DDR5 is nonstandard to begin with and I assume AMD and Intel are using undocumented ECC codes. There might be hints in patents.