It's really quite impressive how bad Intel's track record has been. Would you say it's a broad cultural problem within Intel? Bad incentives?

(I'b be interested if someone could come up with a list of all of Intel's failed ventures. StrongARM, Optane, Altera... Obviously some of these are par for the course for such a large company as Intel, but Intel still seems to stand out)

(I know one reason Apple is so secretive about its ventures is because it knows many of them won't pan out, and it knows that due to its size anything it does has huge repercussions, and wants to avoid that)

They have had lots of things they stopped doing, the graphics chip I was involved in (82786) was one, the speech chips, the iAPX431, the modem chips, their digital watch was an early one.

I always saw it as an exceptionally low tolerance for risk. When I was their the 386 had just fabbed and I was one of the people watching when the very first chip was powered up and it actually worked (which amazed pretty much everyone). Sun Microsystems was a little startup in Mountain View using the 68000 and getting some traction I suggested to Intel that if they used the graphic chip I was working on and the 386 they could build an Intel branded "Workstation" and both replace the VAXStations they were using for CAD work internally and sell them as part of Intel's initiative to become a "systems company." I got a response to my memo[1] from Dave House who was later CEO but at the time just the head of Microprocessor Operation (MIPO) Marketing explaining to this lowly NCG (new college grad) that Workstations were not much of a market and Intel was only interested in pursuing the "big" opportunities. Six months later I joined Sun (just after they IPO'd sadly) and didn't look back. :-)

[1] Yes memo, as in typed up and printed out and put in a manilla envelope where on the last line of the front had it coming from Dave and being addressed to me. And yes, it started as a memo I had printed out and given to my manager because while Intel had "heard" of electronic mail they preferred the "durability" of actual mail and forcing people to use actual mail cut down on "frivolous" communications.

I have wondered if leadership didn't understand the Gartner Hype Cycle, because a lot of projects seem to get killed after the investments but before significant success was even possible (the Trough of Disillusionment).

During my tenure I witnessed several failed initiatives. Itanium, Wimax, Digital Home, x86 phone (android), LTE modem. Imagine the billions wasted.

* They got their LTE modem into the iPhone 11 but just couldn't compete. * ARC GPUs would have been competitve if they had be launched a year or two sooner and its stagnancy is widley due to lack of funding since the market was dead during launch and we were in a massive market pullback where they were ultra hesitatnt to spend ANY money. (massive layoffs too) * Optane was a great product and had a good roadmap, but they were burning cash waiting for adoption and their customers had decoupled their memory and storage from the physical layer to mitigate limitations of NAND ssd so much that they didn't see the price as worth it, despite the obvious latency and endurance benefits that it had over even SLC NAND drives.

Sometimes they just miss the market for otherwise good products.

it wasn't "just couldn't compete", those modems were horrible. the speed was lower than the Qualcomm that managed to be shipped in some of the iphones (from 8-11), and the connections were extremely flaky. I had a 9 with an intel modem, and it was abysmal compared to the previous iPhones I had owned.

that apple went back to Qualcomm, bought the intel division, and still is shipping Qualcomm modems says a lot -- it's still just not there.

And this was even before being slower even with strong signals.

So slower and noticably worse range. Modems are hard and take a long time to have small things ironed out here and there. Small things add up.

I have a hard time believing that Intel will succeed at being a foundry this time around given how many failed prior attempts they have made. The foundry model is incompatible with the high margin duopoly CPU vendor model. What will prevent Intel from scheduling their own high margin products in fabs over foundry work from other companies? They will always have a business incentive to deprioritize their foundry customers when push comes to shove.

Reading some of the comments made by TSMC are enlightening. One of the reasons TSMC provided for their ability to succeed when Intel was flailing with their 10nm+++++ process is that TSMC runs experiments 24/7. This allows TSMC to run more experiments per day/week/month than Intel. I would really like to know when Intel starts running 3 shifts of process development engineers at a single fab to iterate faster, as that would be a true sign that meaningful change has occurred inside the beast.

I don’t care how well Intel executes and how well your launch market functions, if you’re selling a product that caters to business travelers and users, you had better actually be willing to sell the thing, across a large swath of the country, or it will fail regardless of how good it is.

Given the strong assumptions it was making about compile-time instruction scheduling, I'd have expected them to de-risk the project first. I.e., get a suitable compiler working, and get some benchmark results on a simulator.

"Anyway this chip architect guy is standing up in front of this group promising the moon and stars. And I finally put my hand up and said I just could not see how you're proposing to get to those kind of performance levels. And he said well we've got a simulation, and I thought Ah, ok. That shut me up for a little bit, but then something occurred to me and I interrupted him again. I said, wait I am sorry to derail this meeting. But how would you use a simulator if you don't have a compiler? He said, well that's true we don't have a compiler yet, so I hand assembled my simulations. I asked "How did you do thousands of line of code that way?" He said “No, I did 30 lines of code”. Flabbergasted, I said, "You're predicting the entire future of this architecture on 30 lines of hand generated code?" [chuckle], I said it just like that, I did not mean to be insulting but I was just thunderstruck. Andy Grove piped up and said "we are not here right now to reconsider the future of this effort, so let’s move on". I said "Okay, it's your money, if that's what you want." Suddenly this came up again later in another guise but again Andy shut me off, he said "we're not here to discuss it". Gordon Moore is sitting next to me and hasn’t said a word, he looks to all intents and purposes like he's asleep. He's got his eyes closed most of the time, you think okay, the guy's tired, he's old. But no, 20 minutes into this, he suddenly opens his eyes and he points to me and he asks, "did you get ever get an answer to your question?" and I said, "actually no, none that I can understand". Gordon looked around and says, "how are we planning to move ahead with this, if the answers don't make sense?" and this time Andy Grove said to him "We’re not here to discuss that, Gordon"."

Big laugh at the claim of intel having a exceptionally low tolerance to risk when they're the only semi company left still running their own fabs, decades after AMD sold off their own for being too risky of a venture to keep running by themselves. And every fab company out there will vouch for how risky that line of business is. Even more so to pour billions into a business like this while knowing Samsung/TSMC might beat you.

More correct would be that Intel has a low tolerance to risk for things that are way outside of their core competencies which have traditionally been designing X86 CPUs and fabbing them, and that's mostly it.

I commend them for not giving up on advancing their fab nodes despite the massive issues and setbacks(they could have spun it off like AMD did), and for building the ARC GPUs and keep improving them despite low sales.

Yes and even within that they are risk averse, no need to look beyond 10nm and their reluctance to EUV.

So they are really risk averse and they just want their success to continue infinitely. In fact, contrary to Pat G claiming that Nvidia is lucky; it's really Intel which was lucky.

>> commend them for not giving up on advancing their fab nodes despite the massive issues and setbacks(they could have spun it off like AMD did), and for building the ARC GPUs

even if the turn around time in semi market is longer, the way they faltered on their Arc timelines and no encouraging signs of their new fab nodes is not commendable!

Wasn't there an article on HN 2 days ago about Intel pushing 2 new technologies simultaneously in their next node? (ribbon gate and backside power?)

When I read "ribbon gate" just now, I assumed you were referring to some scandal.

Let's hope that's not prescient :)

Sure, Intel fucked up along the way, and it's easy to point fingers and laugh from the comfort of the armchair at Intel tripping over massively complex engineering challenges, but if designing and building successful GPUs and sub-7nm fabs was easy, everyone would be doing it.

Further, neither do the facts nor my comment in any way implies building GPU's is easy. OTHO, when a company like Intel with their massive competitive advantage (when their fabs were the market leaders) thus leading to financial muscle fritter it away in what is supposedly their strength (fabs), don't you think that they in fact deserve to be laughed at?

Is it that unfortunate? Because if you knew how difficult semi fabrication or GPU design is, you probably wouldn't say these failures are such big deals worth pointing out as negatives, but part and parcel of the process of solving such complex problems only 3 players worldwide have mastered.

Do you see Nvidia trying to fab chips? Do you see TSMC trying to design GPUs? Imagine Intel is doing both at the same time. Of course they will fail at points along the way, the important thing is they stay in the game to provide us with competition.

Actually from what I heard, their failures with their Intel 7 was partly due to trying too many unproven technologies - i.e. they pulled a Zumwalt. With their current Intel 4 & 3 I heard they were more conservative.

Everything about bleeding edge semi fabbing is unproven technology.

What was more shocking is how long them seemed to be in denial before putting contingency plans in place.

He said this some time in the 80's to early 90's as a defence for their expensive commitment to still be running their own fabs when most big semi companies like Motorola were selling off their fabs and going fabless because it was eating their resources and it was impossible to compete with the likes of TSMC on node shrinks and value.

So even without Intel screwing with them in anti-competitive ways, they could not have kept their fabs competitive much longer. The writing was already on the wall way back then but Jerry Sanders was just being stubborn.

[1] https://archive.is/igC4r

So I don't think it's as direct a link as you seem to claim. Maybe it was the right decision if AMD had the money to keep it going. But it will likely forever be one of those questions that has no solid answer either way.

IMHO Ruiz cut back on engineering and increased marketing. Then purchased ATI which I though was an odd or even dumb move (it was not). But that expensive purchase along with the failure of bulldozer almost killed the company. That's why they spun off Global Foundries - to stay alive.

As a former Intel-er myself (during Craig Barrett, Paul Otellini times) I would disagree. Intel took bold and foolish bets bying DiaLogic, selling Xscale, betting on WiMAX mobile technology while fighting LTE backed by all telcos. I would characterize Intel's risk management as "passive-aggressive".

It's a very tight market out there. TSMC was able to make it with very tight partnerships with OEMs and I doubt Intel can pull off something like that.

Tragically, I wouldn't bet on it. In fact, I'd be shocked if that were to happen.

Recent hindsight with TSMC makes it look "easy", but it's incredibly uncertain simply due to the complexity and number of pieces that have to align.

Unfortunately, this seems unlikely. The FPGA vendor tools are a complete shit show and open source tools would be greatly welcomed - they're doing really well in the Lattice/ICE40 space but those are small FPGAs. But Altera and Xilinx don't seem at all inclined to encourage the development of open source alternatives.

When it is almost impossible to develop for, you only get big contracts because nobody else has the resources to design products for it. On the other hand, with good and free design tools the toy projects done by hobbyists and schools can serve as the catalyst for using it in medium-scale projects.

There are plenty of applications imaginable for something like Intel's SmartNIC platform - but you're not going to see any of them unless tinkerers can get their hands on them.

Xilinx, for example, used to be very friendly about making really cheap or even free FPGAs available to academic users. This is because those users lead either directly to design wins (some academic designs go big, NSF style) or they become corporate users who are familiar with Xilinx gear.

But the software was crap, and they would have gotten more wins if the software wasn’t so awful.

"EDA software is crap" is so close to an axiom around here that I think Vivado doesn't get the credit it deserves. The synthesis flow has been rapidly modernizing and supports a chunk of VHDL-2019. The bundled simulator still lags on support and features, for reasons that are pretty easy to understand.

That’s too bad. I once got a small pile (8?) of max-spec Virtex-5 chips, for free, FedExed from Xilinx. Xilinx apparently valued them so little that they didn’t even bother putting the full address on the envelope. Tracking it down was fun.

The only remotely supportable way to synthesize images for them was to run a primitive CentOS 5 container on a big server — the Windows version of the tools were still 32-bit, and 4G of address space was too little for the synthesis workflow. Even with the magic 64-bit RHEL/CentOS-only build, it would take 45 minutes or so for the tools to notice any errors during synthesis.

Fun times.

Thanks for the stock tip. The size of a chip can change, and will. Stupidity really tends not to. Great dev tools are incredibly important, and the people using them actually can influence decisions on which parts to use.

The whole thing definitely seems symptomatic of Intel's extreme caution. I wonder why they didn't apply the same caution when buying Barefoot. Intel obviously didn't have a great idea on how to leverage them.

This is all in stark contrast to AMD buying Pensando, a company that my SO works for. It makes sense for AMD to acquire Pensando to expand their data center offerings and compete directly with Intel. I think AMD made a smart buy.

> It still seems like a ridiculously foolish idea, considering how much money Intel spent acquiring Barefoot

Acquiring companies in order to kill them is a horrible business practice but not unusual. The thing that makes no sense to me is why they kept it going for three years before killing it. If they bought it in order to kill it, they should have done that before spending another hundred million on it.

At this point, if it's not about x86 cpus, listening to Intel's roadmaps seems foolish.

Internal politics?

Presumably the internal team(s) with overlap were against the acquisition.

But it was likely easier to see if the integration failed on its own before spending the political capital to kill it.

Folks forget executives at large companies usually optimize for "my career" over "the company."

So insane. It's always better in invent the next big thing that changes the market than a competitor, even if it kills another product of your own.

What do you mean by this? When working with a fab you get to know their design rules and that's about it.

The point being, there's no world where a fab would worry about sharing their design rules.

> Engineers needed manufacturing process information to verify that designs were free from systematic yield limiters, but foundries were reluctant to distribute process information that could reveal best practices and trade secrets. Encryption enabled the protection of selected design rules, process data and other information while still giving customers the details they needed.

> In this discussion, you must understand that the required protection is much more than just an obfuscation of rule definitions so they are no longer human readable. The process also includes the encryption of related files and control over all the outputs from the tool environment that provide information about any checks.

https://www.techdesignforums.com/practice/technique/protecti...

The design rules themselves could yield info to competitors about what processes are being used in the upcoming gen.

https://www.eejournal.com/article/intel-plans-to-spin-off-fp...

I remember finding it rather funny at the time that Altera would go "full circle" so quickly.

The amount of market I saw dissolve for Altera in a puff was incredible. To this day one of the most shortsighted corp decisions I have ever witnessed.