This is apologetics.

The real reason is the hardware vendors are entrenched and don't make money off the software at all. The situation is exactly the same as it was in the proprietary compiler space before gcc (and then clang) - no incentive to improve or open source the compilers -> no access to good tools -> proprietary tools remain only option.

Yosys though, being an open source attempt, is just making unforced errors, hence my ranting and raving in the other thread.

You're talking about FPGA tools but this thread is about VLSI design where the major EDA vendors (Synopsys, Cadence, and Mentor) don't sell hardware(*) and *do* make a lot of money from software.

(*) Excluding emulators or simulation accelerators.

> You're talking about FPGA tools but this thread is about VLSI design

did you miss the part where the comment i'm responding to is about VTR?

My bad, I thought we were talking about ASIC designers, not VTR developers.