I think it’s more likely these people mainly enjoy designing hardware, not tools for designing hardware (aka software). Learn to use a tool, and use it. It’s a hammer, start driving nails
Software development is unique in that tools for building software are also software. This hammer is great and all, but I make hammers, and I know this one could be better
Re:VLSI Physical Design
by mathisfun123 on Wednesday September 27, 2023 @03:27PM
(#37679959)
This is apologetics.
The real reason is the hardware vendors are entrenched and don't make money off the software at all. The situation is exactly the same as it was in the proprietary compiler space before gcc (and then clang) - no incentive to improve or open source the compilers -> no access to good tools -> proprietary tools remain only option.
Yosys though, being an open source attempt, is just making unforced errors, hence my ranting and raving in the other thread.
You're talking about FPGA tools but this thread is about VLSI design where the major EDA vendors (Synopsys, Cadence, and Mentor) don't sell hardware(*) and *do* make a lot of money from software.
(*) Excluding emulators or simulation accelerators.
Re:VLSI Physical Design
by mathisfun123 on Wednesday September 27, 2023 @04:55PM
(#37681168)
> You're talking about FPGA tools but this thread is about VLSI design
did you miss the part where the comment i'm responding to is about VTR?
I mean just go look at that post from yesterday where I complain that yosys uses C++ to script flows and the response to the complaint - I'm starting to think these people just enjoy being miserable.