x86 is locked down by Intel and AMD, and ARM demands tribute-- I mean license fees for ARM. That leaves only RISC-V for those who want to make their own processors without paying someone for the privilege. That's the value add.

You could always go for Xtensa, PIC/AVR, or 68k. Still plenty of those around - although ARM has rapidly been eating their lunch the last few years.

PIC and AVR (along with 8051 and 6502 based designs) are still used in current consumer products reusing older designs. Yes, ARM Cortex-M0 can cost the same while offering 2x the processing processing power, but redesigning the PCB and rewriting the entire codebase for a new MCU would offset the processing power gains, which are not needed anyway.

Most white-label consumer goods just need to poll some keypad buttons, react to some interrupts, and turn a relay ON/OFF depending on a simple state machine reading an ADC, where an 8-/16-bit PIC/AVR is more than enough. If they have a built-in DSP even better.

A 6502 or 8051 can do the job but their prices haven't dropped a lot.

You can get a 48 MHz RISC-V from WCH (a big 8051 supplier) or Cortex-M0 from Puya for $0.10 to $0.15 depending on whether it's an 8, 16, or 20 pin package. Both the CH32V003 has 2 KB SRAM and 16 KB flash, and the Puya 3 KB SRAM and 20 KB flash. You get the above prices for the WCH at qty 50 (i.e. $5 - $7) on their Aliexpress store, plus a couple of bucks shipping.

Being "too powerful" for the job is irrelevant if it's cheaper anyway. Plus easier to use because both use standard GCC/LLVM, support debugging etc.

Once RISC-V gains market share, Intel and ARM will react, lowering fees and opening their platforms, if needed. They will try to block the addition of value.

If that happens it's a win for everyone, but unlikely in practice, given their business models. Don't see how they can block RISC-V.

But an additional advantage for RISC-V is that it's a clean slate specification and very simple at its core, and that enables a lot more use cases that would otherwise be impossible due to legacy cruft.

Blocking won’t happen, but remember theses companies also detain a massive patent portifolio which is hard not to break while implementing similar techniques.

Despite personally I really wish it was different, there is a lot of fragmentation already in RISC-V and I feel it only tends to grow given managers will always push to create some internal secret sauce.

What I like about RISC-V is that it's not just open for the sake of being open, but actually a well-designed architecture. Practical & effective from embedded to enterprise & beyond.

For example, modularity: most other ISAs have had heaps of extensions bolted onto the ISA over time, in order to produce fast CPU cores. Things like MMX, SSEx, AVX, ARM's Thumb, Neon, etc etc.

So if (for example) you want x86 core with some form of AVX, you get at least a 64 bit, 2-core cpu with SSEx, single & double precision floating point, a long list of addressing modes, support for i386 software/memory models, the works. If you want a 'minimal' core, you're looking at ancient 386 or 486, and neither AMD or Intel will bake those for you.

Over in the RISC-V camp, a vendor can take a minimal core, add only those extensions needed for a System-on-Chip's intended uses, bring that to a foundry, and have software toolchain in place the day silicon is taped out.

Instruction encoding is mostly (entirely?) the same between 32-bit and 64-bit versions. 64-bit simply having wider registers. Compressed "Thumb" instructions translate 1:1 to instructions with the standard 32-bit encoding. Bit fields encoding source & destination registers are always in the same place. Sign extension is trivial. No myriad of obsolete memory models. Etc, etc, as I said: well designed architecture.

All these goodies enable efficient / small / cheap hardware, and relatively easy software support.

In that case the main strength of RISC-V would be Chinese companies since it is theoretically sanction resistant.

> That leaves only RISC-V for those who want to make their own processors without paying someone for the privilege. That's the value add.

I don't think that's the value add for larger companies who want to pay and get a high level of support, it's that there are multiple vendors in theory and practice.

> "That leaves only RISC-V for those who want to make their own processors without paying someone for the privilege."

OpenSPARC? OpenPOWER?

Why would someone use OpenSPARC rather than riscv? Seems like the Linux distros have some a-tier support for riscv64, or will soon. Debian supports SPARC right? Anyone else?

That's not even getting into upstream testing. I imagine there is more development attention to riscv tooling e.g. GCC, llvm, glibc, musl, util-linux, et cetera.

OpenSPARC/POWER is the reason why I am not too excited about RiscV. We have had open GPL designs for close to 20 years and they just sort of went nowhere. RiscV seems to be something neat for those that design processors or work with them low level but for the general person I do not think it will result in anything amazingly different.

SPARC was only open for 32 bit and POWER was not actually open until many years after RISC-V.

> RiscV seems to be something neat for those that design processors or work with them low level but for the general person I do not think it will result in anything amazingly different.

For the general person of course nothing technical matters. But for the industry it matters a whole lot.

SPARC only has a 32bit version that's open. Its really not a option. Even if want to use something 32bit, you would like some upgrade path for the future. And technically its also just worse in pretty much every way. After the standardisation there was very little continued progress and investment.

OpenPOWER only became open many, many years after RISC-V was open. OpenPOWER was basically just a marketing name, it was not actually open. Once RISC-V was opened for real, eventually the pressure was on OpenPOWER to actually be opened.

However by the time they opened it up RISC-V already had all the momentum both commercially and in terms of open development.

OpenSPARC seems to have had open 64-bit designs released before RISC-V was launched?

"In March 2006, the complete design of Sun Microsystems' UltraSPARC T1 microprocessor was released-in open-source form, it was named OpenSPARC T1. In early 2008, its successor, OpenSPARC T2, was also released in open-source form. These were the first (and still only) 64-bit microprocessors ever open-sourced. " -https://www.oracle.com/servers/technologies/opensparc.html

The 32bit is a standard 'IEEE Standard 1754-1994'. The 64 bit implementation was released by SPARC International but its not a standard.

As far as I know without joining SPARC International you are not allowed to commercially use SPARC 64bit commercially.

There might be open implementations, but that doesn't mean you can be sued for using the architecture.