But an additional advantage for RISC-V is that it's a clean slate specification and very simple at its core, and that enables a lot more use cases that would otherwise be impossible due to legacy cruft.
Despite personally I really wish it was different, there is a lot of fragmentation already in RISC-V and I feel it only tends to grow given managers will always push to create some internal secret sauce.
For example, modularity: most other ISAs have had heaps of extensions bolted onto the ISA over time, in order to produce fast CPU cores. Things like MMX, SSEx, AVX, ARM's Thumb, Neon, etc etc.
So if (for example) you want x86 core with some form of AVX, you get at least a 64 bit, 2-core cpu with SSEx, single & double precision floating point, a long list of addressing modes, support for i386 software/memory models, the works. If you want a 'minimal' core, you're looking at ancient 386 or 486, and neither AMD or Intel will bake those for you.
Over in the RISC-V camp, a vendor can take a minimal core, add only those extensions needed for a System-on-Chip's intended uses, bring that to a foundry, and have software toolchain in place the day silicon is taped out.
Instruction encoding is mostly (entirely?) the same between 32-bit and 64-bit versions. 64-bit simply having wider registers. Compressed "Thumb" instructions translate 1:1 to instructions with the standard 32-bit encoding. Bit fields encoding source & destination registers are always in the same place. Sign extension is trivial. No myriad of obsolete memory models. Etc, etc, as I said: well designed architecture.
All these goodies enable efficient / small / cheap hardware, and relatively easy software support.