Ao486_MiSTer: i486 core for the MiSTer FPGA gaming system

Re:Ao486_MiSTer: i486 core for the MiSTer FPGA gaming system by mk_stjames on Sunday March 05, 2023 @01:06AM (#35027255)

I've written some small CPU cores in Verilog and used Logisim to design some small FPGA circuits but I can't fathom writing out an entire 486. Any info on what sort of project management or automation tools are being used to generate all this Verilog? Because this is literally tens thousand+ lines to define the functionality of a 486 and I can't imagine someone writing out register tables and kept track of naming the pipelining all by hand. I'm guessing something like Vivado or some other IDE is used to help manage everything? I can't tell from the source in RTL. I find this use of FPGAs to replicate older CPUs/SOCs fascinating.

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Re:Ao486_MiSTer: i486 core for the MiSTer FPGA gaming system by anewhnaccount2 on Sunday March 05, 2023 @01:36AM (#35027407)

There is a file generated by Quartus at https://github.com/alfikpl/ao486/blob/df6eba123654fdf3e3058c... I'm not sure, but it does seem mostly manual. I tend to agree that RTL is somehow particularly mind numbing. I would guess that in order to keep track of things you may have a large block diagram on paper beforehand.

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Re:Ao486_MiSTer: i486 core for the MiSTer FPGA gaming system by userbinator on Sunday March 05, 2023 @01:33AM (#35027399)

Based on the .q* files, I'm pretty sure it's https://en.wikipedia.org/wiki/Intel_Quartus_Prime

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Re:Ao486_MiSTer: i486 core for the MiSTer FPGA gaming system by sweetjuly on Sunday March 05, 2023 @03:00AM (#35027781)

Many companies do just write entire modern SoCs in straight Verilog (maybe with some autogenerated Verilog hacked in there) with no other major organization tools aside from the typical project management stuff. The load-store unit of a modern CPU alone easily exceeds 10k lines of Verilog. It's a similar thing as people who work with kernels—after all, the page table management code in a modern operating system like Linux is absolutely monstrous but still people are able to understand it well enough to be able to make the changes they need and get out.

If you are interested in other languages which hope to make this sort of stuff easier, I'd recommend taking a look at design productivity languages like Chisel and it's associated Chipyard [1], SpinalHDL [2], and Bluespec [3]. Each of these are meant to make defining extremely complex hardware more manageable for humans and there's a lot of interesting work going on right now with each of them.

[1] https://github.com/ucb-bar/chipyard

[2] https://github.com/SpinalHDL/SpinalHDL

[3] https://github.com/B-Lang-org/bsc

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Re:Ao486_MiSTer: i486 core for the MiSTer FPGA gaming system by mk_stjames on Sunday March 05, 2023 @03:51AM (#35027986)

I'm more curious if there is something that makes visualizing the Verilog easier... for instance, I've done some small projects where I used Digital [0] (which is so unfortunately named, but awesome) to put blocks of Verilog into the visual representation and then connect my blocks together (like ALU, block ram, registers etc) and run simulation. But the problem is taking all that out back to Verilog and then doing my synthesis with Yosys is a manual chore.

I am wondering if there is some sorta... IDE that is letting people inspect projects with lots in individual Verilog files quickly and show the structure visually (and manage test benches run Icarus and GTK wave etc). I haven't seen this outside of vendor-specific tools like Xylinx's Vivado and I'm wondering if I am just missing something or if that kinda of IDE doesn't exist in any open source tools just yet.

[0] https://github.com/hneemann/Digital

Edit- and yes I get that I'm probably just not used to the management of Verilog codebases and it's no different than software packages with lots of 'modules' and you just work on a module at a time and it isn't that crazy. But I find it odd that there aren't at least some more viz tools, considering functions of a CPU are so 'block' based... I'd love to be able to load up the RTL folder of one of the CPU projects and see how all these Verilog modules are connected to one another and to the top level. Size of the busses, number of instances, etc. As though it were a Logisim project.

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Re:Ao486_MiSTer: i486 core for the MiSTer FPGA gaming system by rzzzt on Sunday March 05, 2023 @04:30AM (#35028134)

I'd have also pointed you to Xilinx, more specifically their discontinued ISE product which we used for a university course. It did provide a schematic-style high level overview of how modules are wired together and also had a simulator which you could run from the IDE directly.

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Re:Ao486_MiSTer: i486 core for the MiSTer FPGA gaming system by RobotToaster on Sunday March 05, 2023 @04:46AM (#35028205)

Icestudio sounds similar to what you're looking for, but I'm not sure if it works with existing code.

https://github.com/FPGAwars/icestudio

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Re:Ao486_MiSTer: i486 core for the MiSTer FPGA gaming system by tails4e on Sunday March 05, 2023 @07:20AM (#35028971)

I reguarly use Vivado elaborated design view to browse RTL hierarchy. The schematic view, signal trace, etc is the best I've seen. You can also automate it with tcl, so I've used it to auto highlight clock domains in different colours, so you can see where crossings happen, etc.

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Re:Ao486_MiSTer: i486 core for the MiSTer FPGA gaming system by cmrdporcupine on Sunday March 05, 2023 @12:14PM (#35031574)

Doesn't help with visualization, but there's a SystemVerilog/Verilog plugin for Jetbrains IDE (Clion etc) that is actually really helpful. Does renames, code completion, structural view, etc. like what you'd expect from a real IDE. I far preferred it to working in Vivado.

When I was using it, I used it with FuseSoC, and only dropped into Vivado when I needed to muss around with their "IP integrations, etc.

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Re:Ao486_MiSTer: i486 core for the MiSTer FPGA gaming system by fentonc on Sunday March 05, 2023 @09:15AM (#35029751)

Many CPU/SoC systems could be made vastly simpler while maintaining binary compatibility if you're willing to sacrifice performance/area. Anything that's not visible from the ISA level can be implemented however one wants. You can cram more logic per pipeline stage, stall instead of having complicated bypass logic, etc. Much of the complexity of modern circuit design comes from the desire to eek out every last percent of performance from a process, which is completely unnecessary for a historical project like this.

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