Doesn't help with visualization, but there's a SystemVerilog/Verilog plugin for Jetbrains IDE (Clion etc) that is actually really helpful. Does renames, code completion, structural view, etc. like what you'd expect from a real IDE. I far preferred it to working in Vivado.

When I was using it, I used it with FuseSoC, and only dropped into Vivado when I needed to muss around with their "IP integrations, etc.