Re:Ask HN: If the CPU redesigned today, with no legacy incen...
by eimrine on Friday March 03, 2023 @07:45AM
(#35008838)
I refuse to understand your C programming point, but answering your question, a computer might be a Lisp machine and/or having von-Neumann architecture instead of Harvard one. CPU might be more multithread and GPU might be better suited for such things as calling eval().
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Re:Ask HN: If the CPU redesigned today, with no legacy incen...
by t-3 on Friday March 03, 2023 @10:46AM
(#35011098)
> having von-Neumann architecture instead of Harvard one.
I think you got that backwards. Von Neumann is mainstream and a few MCUs use Harvard architecture.
Re:Ask HN: If the CPU redesigned today, with no legacy incen...
by eimrine on Friday March 03, 2023 @11:03AM
(#35011349)
So why a CPU cache (L1 L2 L3) has 2 halves, one for code and another for data?
Re:Ask HN: If the CPU redesigned today, with no legacy incen...
by t-3 on Friday March 03, 2023 @11:24AM
(#35011623)
Can you directly choose what goes into the cache or is it just a technical optimization? Which instructions read and write the cache?
Re:Ask HN: If the CPU redesigned today, with no legacy incen...
by zerohp on Friday March 03, 2023 @11:52AM
(#35012046)
You can directly choose what is available on the instruction side by using the XN (aka XD) permission bits in the page table. Other mechanisms exist to make pages readable by instruction fetch but not readable by the data side.
Von Neumann vs Harvard is a pointless discussion. Both are too simplistic describe modern architectures.
Re:Ask HN: If the CPU redesigned today, with no legacy incen...
by LangIsAllWeNeed on Friday March 03, 2023 @12:12PM
(#35012332)
How would you understand the c to architecture connection?
I have read that C ideas are baked into how higher level programming languages work, but modern cpus are a lot more parallel and some other things than most languages fail to account for, so the microcode tries to bridge gap.