It’s built from the bottom up in layers (at least traditionally, I’m not sure how the newer 3D structures for memory are constructed). The bottom layer of silicon substrate is covered in an oxide and etched selectively by photoresist and masking. Further layers are connective layers of metal lines insulated by oxide, with vias connecting metal layers to one another. The same oxide deposition, photoresist, expose, etch process is used for each layer.

Haven't worked in the space in more than 15 years, but as I recall there were dozens of masks - maybe upwards of 50 - when I was doing ASIC.

And I believe there were steps to flatten and I believe effectively sand the surface flat after some layers.

> oxide deposition, photoresist, expose, etch process is used for each layer

Would note that since FinFETs, deposition occurs from the side as well as top.

You can only ever reach exposed surfaces. This means a very complex sequence of adding and removing layers to expose/hide things so that the currently exposed surface features are what you want to change in the current processing step.

The Wikipedia article on CMOS has a very nice illustration of the basic steps of this process: https://en.wikipedia.org/wiki/CMOS#/media/File:CMOS_fabricat... Current processes are much more complex than even that.

Wow, that's a remarkably informative image, thank you @ThrowawayR2.

Steps 7, and especially 8, seem like magic without a good explanation of how they're possible.

That’s because they skip quite a few steps. You would first deposit a photosensitive layer, then expose it wit a pattern of light, which will allow you to selectively open up the parts you want to toch next.

For step 7 for example, you create a masking layer that way, after which you etch away only the exposed parts where source and drain contacts will end up.

For step 8, you do something similar. The openings you’ve etched in step 8 will allow only to dope the contacts, but you need to mask the nmos and pmos separately, otherwise you get the same doping in both transistors.

A lot of the ‘magic’ to make this work is in the materials and chemistry: you need selectivity: etching that only interacts with the exposed parts. In highly scaled finger nodes, the material combinations are very complex as you sometimes want 2, or 3 different material combinations to interact in the way you want, reliably, at nanometer scale.

There are "wells" to tap the components into. You just add successive layers in a very smart way.

Each wafer has only one layer of transistors. They then have many layers of wiring on top. They go through semiconductor manufacturing with one layer of transistors.

For each layer of metal, they go through several steps of deposition of insulator, masking, etching, deposition of metal (often in several passes now), grinding or etching that, and then covering it all up with more insulator and grinding that layer down to produce a smooth surface for the next layer.

Once the chips are complete, 3D stacking is a packaging process. It involves grinding the backsides of the chips down until they are very thin and attaching the dies together using vias that run through the thin remaining silicon layer.

EDIT: Flash memory today has multiple stacked doped silicon layers, but it is a special process that is largely unsuitable for logic.

That's super informative, much better than any other video or article I found, thanks!

Its one of those presentations I come back to and re-watch every now and then, wish there was a 202x version of it.