How does it solve the problem that the FPGA doesn't have a path from the signal-to-observe to the logic blocks?

You can specify the list of signals to observe, which is built into the gateware.

As memory is also limited, you specify a condition like if signal A becomes 0x1234, then log the aforementioned signals for N cycles.

I have to admit I still don't get it. When I try to log the signal using my own signal logger (which I guess is somewhat like that "virtual oscilloscope"), the synthesis tool rejects the design and tells me that I cannot use that signal as an input because the FPGA doesn't have a path from there into the logic blocks. What does LiteX do differently to observe a signal that my own gateware cannot access?

What kind of primitives are you talking about here? In my experience you don't really have to manually instantiate anything other than a PLL or maybe a multiplier unless you're doing something very specialized.

I was specifically thinking about DDR3 related primitives.

Only simulator could check signal to which could not connect physically.

But, you could split project into small parts, connected by some interface (could use triggers or 2-way ram cells), and debug them separate.

Sure, you will loss some capacity, but this is life.

This is not equal to test real solution, because physical arrangement matter, but most probably, you will find most obvious mistakes.