I have to admit I still don't get it. When I try to log the signal using my own signal logger (which I guess is somewhat like that "virtual oscilloscope"), the synthesis tool rejects the design and tells me that I cannot use that signal as an input because the FPGA doesn't have a path from there into the logic blocks. What does LiteX do differently to observe a signal that my own gateware cannot access?

What kind of primitives are you talking about here? In my experience you don't really have to manually instantiate anything other than a PLL or maybe a multiplier unless you're doing something very specialized.

I was specifically thinking about DDR3 related primitives.