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A comment on Parallel Programming for FPGAs. Parent comment
But, you could split project into small parts, connected by some interface (could use triggers or 2-way ram cells), and debug them separate.
Sure, you will loss some capacity, but this is life.
This is not equal to test real solution, because physical arrangement matter, but most probably, you will find most obvious mistakes.
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But, you could split project into small parts, connected by some interface (could use triggers or 2-way ram cells), and debug them separate.
Sure, you will loss some capacity, but this is life.
This is not equal to test real solution, because physical arrangement matter, but most probably, you will find most obvious mistakes.