That is because there is a huge design gap. Intel architecture and design teams have always assumed on the inevitability of their own manufacturing superiority and process advantage and thus never had to really consider where to place transistors for the most benefit, or think really hard on better ways to improve single-thread performance instead of just turning a knob that was invented two decades ago.
In any case, your statement is just plain wrong. Dennard scaling has been dead for a decade now. Planar area decreases with new processes come with increased power density, i.e. new process nodes reduce die sizes but the transistor performance does not improve the way they used to.
source: worked at Intel for CPU design for a decade, then worked on the same things elsewhere using TSMC process
Nobody in CPU design cares about unconstrained power performance. Even at Intel, they never use the PL2 power level as the design landing zone. All modeling is done at much lower power target, even below PL1.
That is to say: unconstrained power performance is not an engineering effort, it is a marketing and SKU differentiation effort. Your “more powerful” statement is a matter of how much power Intel/Apple/AMD/whoever is willing to shove into their piece of silicon, which in turn dictates the form factors and customers they can try to satisfy.
Apple only needs a few watts per big core and still get the peak perf it needs, and put that chip in all the form factors it sells. Obviously if M1 sucked down the kind of power as any Intel chip, it cannot go into an iPad, or a fanless macbook air, without totally compromising performance.
Intel on the other hand needs grossly more watts to hit that same performance, and therefore is losing badly on form factors that care about power: laptops and servers. Some form factors/customers just don’t care, which is why Intel cooks up marketing targeting the gamer market, or the 8-pound laptop market. That’s all fine, just don’t pretend Intel is not getting absolutely hammered on the CPU technical specs for the money-making markets that matter.
BTW, the DIY gamer CPU market does not matter. The 8-pound laptop market does not matter.
The fanboyism runs so deep it's amazing. Let's compare PS5 to GameCube next and talk about Sony's great engineering advantage
Go compare the perf/power curves of the alder-lake cores (both P/E) versus the last-gen Apple cores from TSMC n7+. TSMC n7+ is roughly comparable to Intel 10nm ESF in transistor performance, so it is a fair comparison.
Do your research then get back to me about how the process is entirely responsible for every perf/power difference and we (the silicon design teams) are just identical robots doing the same thing across the board in every company.
I do like how you claim there is no design magic sauce, but then Apple will lose big when Intel/AMD come out with their 5nm equivalents, as in, they found some magic sauce? WTF?
The same MacBook Air can do hour long Skype video calls with ~9% charge consumption, with no discernible heat difference on the body too.
M1 is a different beast.
Why is everyone insistent on comparing Apple’s latest CPUs to Intel’s parts from multiple generations back?
Intel is on 12xxx series now. AMD also has new generation laptop CPUs that perform very well. Let’s compare to those.
The M1 is power efficient but much of that is due to the TSMC process they used. I really don’t understand this desire to make arbitrary comparisons to old Intel CPUs.
Will these be meaningful for you?
The thing is, M1 on air is a relatively low clock speed CPU with passive cooling. 10200K is actively cooled, unlimited beast of its generation. The libraries I use are X86 optimized. Yet the code I’ve written is 25% faster on ARM.
This is significant.
Apple knew this so the M1 has an extremely fast memory system.
Intel’s memory architecture can keep up with the load until I utilize all cores. When I start to use HT cores, neither cache, nor memory can keep up.
I do the both tests (Intel and Apple) both with physical core counts to keep it fair.
So it’s not some run of the mill code.
Curious what you meant here since that part doesnt exist, and if it did it would be near the bottom of the stack for the generation (101xx and 103xx are the low core count i3 and i5 parts).
Written that comment on mobile on a plane, before take-off, so I either typo'd and didn't see, or auto-correct changed it deeming 10200K is more correct than 10700K.
If you look to the original comment where I sparked the discussion, I've mentioned it as 10700K already.
Being able to compete against a consumer high end desktop, even if it's an older one, it's a feat all by itself
> M1 is a different beast.
The M1 has other advantages which are decidedly not rooted in the hardware: software. Apple seems to do profoundly better than Windows and Linux at applications actually using hardware accelerators. This makes a gigantic difference in performance and power efficiency.
On a Windows or Linux system it is not at all a given that even very easily hardware-accelerated tasks, like video decoding, actually use the hardware that's there.
Working on HPC field and with generations and generations of Intel hardware, I can tell you that two node difference (alone) never gives you 25% real world performance in the realm of Intel, let alone theoretical.
Real world performance pretty much always lines up with these estimates. It's the main reason why we have exponential growth in computing power in the first place.
It would be a more fair comparison to compare the M1 to AMD's ZEN 4, which should be coming out next quarter.
[1] https://www.tsmc.com/english/dedicatedFoundry/technology/log...
This is jumping from Intel's heroically old 14nm+++++++++++++++ to a brand spanking new TSMC process. It might be on the order of 4 to 6 times denser.
We've seen how the latter went until AMD came back to the game.
TSMC 5nm is better, but AMD is not there yet.
I have a list of instructions per clock from SPECINT results which I compiled from Web sources. (I didn’t verify the results myself.) I added in rumored future processors with their highest rumored performances:
Cortex-A73 (ARMv8-A) 64.4
Pentium M 69.0
Bulldozer (AMD FX) 76.2
K10 (Phenom II) 76.7
Goldmont Plus (Atom 3rd gen+) 77.5
Core 80.0
Bobcat 81.3
Nehalem 90.0
Cell (PS3) 93.5
Jaguar (PS4) 93.5
Sandy Bridge 100.0
Tremont (Atom 4th gen) 100.7
Ivy Bridge 105.8
Cortex-A76 (ARMv8.2-A) 114.7
Zen 115.9
Haswell 117.6
Zen+ 119.3
Gracemont (Atom 5th gen) 120.8
Broadwell 121.5
Skylake 124.0
Zen 2 139.8
A10 (ARMv8.1-A) 139.8
Cortex-A77 (ARMv8.2-A) 141.0
Sunny Cove Ice Lake 146.3
Cypress Cove Rocket Lake 147.6
Zen 3 167.4
Golden Cove Alder Lake 175.6
A11 (ARMv8.2-A) 186.0
Cortex-X2 (ARMv9-A) 190.2
Rumored Golden Cove+ Raptor Lake (’22) 193
Rumored Zen 4 (’22) 207
A12 (ARMv8.3-A) 213.8
Rumored Ocean Cove (’23) 223
A13 (ARMv8.4-A) 235.0
A14/M1 (ARMv8.5-A) 236.7I find the different balances of performance and efficiency cores interesting. I’d love to have a lot more Icestorm cores on a Mac to play with background tasks that don’t need the firestorm ones.
On the Intel side, I’m also disappointed by not having the option to implement the missing instructions in software.
But even being one behind, it outperforms M1, with lower efficiency. Thus reasonable to speculate that a process node advancement would at least put Intel's chip on par with M1 on both perf and efficiency
We'll see, but I highly doubt that Intel-at-equivalent-of-TSMC-5nm will be performance/watt competitive with the M1. Apple gets that power efficiency via an extremely wide-and-deep design that intentionally trades off a surprisingly low max clock ceiling (3.2GHz) for power efficiency while maintaining an absurdly high IPC (something like 75% higher than Intel's IPC at only one process node smaller) that makes it much more competitive on performance than conventional industry wisdom ever expected (there is and has been for years a strong belief that a design as wide as Apple's would be grossly inefficient because you could not possibly extract enough instruction level parallelism to keep so many decoders/execution units saturated -- hence we've spent over a decade with 4-5 wide frontends being the "practical maximum" that allows them to still target ~5GHz turbo speeds, which was believed to be basically the best/only path to high performance within what was believed to be the limit of "achievable" IPC. The M1 blows these fundamental assumptions out of the water).
So Intel makes conventional design decisions that make up the performance of their lower clock-for-clock IPC by turboing well north of 5GHz, at the cost of consuming something like 7x the max power of the M1. A single node shrink isn't going to buy them a 75% increase in IPC (their last 4 or 5 node shrinks combined haven't bought them that much IPC increase), so Intel@equivalent-of-TSMC-5nm still going to have to burn power like crazy to stay competitive on performance, and that's going to cost them efficiency that the node shrink just can't paper over.
It will lead in absolute perf, but its not going to be nearly as efficient.
Intel has had 256-bit dual-issue FMA since Haswell (2013); that's 32 flops/cycle/core. AVX-512 doubled the vector length for Xeon Phi and was generally available in 2017 Skylake.
[1] https://www.tomshardware.com/uk/news/ryzen-7-5800x3d-vs-core...
It's 90% the process node. There is no magic design sauce that makes those chips better.
The big/little design change did seem to improve performance quite a bit for Intel, even using the same manufacturing node as before