Apple knew this so the M1 has an extremely fast memory system.
Intel’s memory architecture can keep up with the load until I utilize all cores. When I start to use HT cores, neither cache, nor memory can keep up.
I do the both tests (Intel and Apple) both with physical core counts to keep it fair.
So it’s not some run of the mill code.
Curious what you meant here since that part doesnt exist, and if it did it would be near the bottom of the stack for the generation (101xx and 103xx are the low core count i3 and i5 parts).
Written that comment on mobile on a plane, before take-off, so I either typo'd and didn't see, or auto-correct changed it deeming 10200K is more correct than 10700K.
If you look to the original comment where I sparked the discussion, I've mentioned it as 10700K already.
Will these be meaningful for you?
The thing is, M1 on air is a relatively low clock speed CPU with passive cooling. 10200K is actively cooled, unlimited beast of its generation. The libraries I use are X86 optimized. Yet the code I’ve written is 25% faster on ARM.
This is significant.