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Re:The x86 architecture is the weirdo, part 2 by titzer on Friday April 22, 2022 @09:39AM (#31121400)
These are all microarchitectural things that should not be surfaced in language, IMHO. This is why compilers exist, to raise the level of abstraction. For example, other than sidechannels (i.e. Spectre), OOO is not observable, nor is ILP or cache hints. Delay slots are observable at the ISA level but typically compilers do the work of dealing with them. Thank god delay slots didn't make it into programming languages; they were a wart of ISA design surfaced because of a lack of decent branch prediction. Can you imagine if you had a bizarre feature where the next line of code after a branch still executed even if the branch was taken? That'd be bonkers.
Re:The x86 architecture is the weirdo, part 2 by SuchAnonMuchWow on Friday April 22, 2022 @10:06AM (#31121693)
OOO is definitely observable when dealing with multithreading.

That's why you have things like memory order constraints on atomic operations in C, and why you need to be extremely careful with how you place things like memory fences when doing anything fine-grained between several threads.

Re:The x86 architecture is the weirdo, part 2 by titzer on Friday April 22, 2022 @10:54AM (#31122326)
Fair point, but I'd qualify that OOO is only observable for racy programs. In languages with shared memory concurrency, but safety, races are either statically disallowed (Rust), or their results are constrained by a (weak) memory model. Java, e.g. only makes rough guarantees that you don't see out-of-thin air values and that you can't violate the type system. Java also is a little stricter around volatile memory access (they are sequentially consistent, iirc). Also worth noting, some reorderings that you see are not due to hardware, but due to compiler optimizations. Compilers have to obey the memory model, too.

Generally, most programmers shouldn't need to be reasoning about OOO or memory order and be using fences. Rather, they should use libraries that are written by experts that use extra-lingual mechanisms (like compare-swap or fences) to guarantee a higher contract.

Re:The x86 architecture is the weirdo, part 2 by toast0 on Friday April 22, 2022 @12:08PM (#31123444)
> Fair point, but I'd qualify that OOO is only observable for racy programs.

I mean, you're basically saying that it's only observable if you care to observe it.

Re:The x86 architecture is the weirdo, part 2 by zozbot234 on Friday April 22, 2022 @11:16AM (#31122641)
Rust has atomic types that can observe races. Such "racy" code is useful because some concurrent code doesn't need the strictest guarantees (sequential consistency). Though, compared to C, Rust does not use the "Consume" memory ordering because so far it has turned out to be ill-defined.
Re:The x86 architecture is the weirdo, part 2 by titzer on Friday April 22, 2022 @11:39AM (#31122967)
AFAICT those can't observe OOO of CPUs, just nondeterminism from interleavings different threads. I.e. they will give you sequential consistency unless you have other, worse races.
Re:The x86 architecture is the weirdo, part 2 by zozbot234 on Friday April 22, 2022 @11:53AM (#31123213)
Sequential consistency is absolutely optional, there are several other possible memory orderings that are far weaker. When programs involve multiple atomic locations concurrently, atomicity is only preserved at each separate location.
Re:The x86 architecture is the weirdo, part 2 by gumby on Friday April 22, 2022 @10:28AM (#31121987)
Think about it the other way around: if the language were sufficiently high level that the compiler could give the CPU more opportunities for OOO. C incorporates too many assumptions about the PDP-11. Sometimes they are harmless (the ++ operator) and sometimes disastrous (memory model).
Re:The x86 architecture is the weirdo, part 2 by AnimalMuppet on Friday April 22, 2022 @01:01PM (#31124445)
> Can you imagine if you had a bizarre feature where the next line of code after a branch still executed even if the branch was taken?

I seem to recall that there was a mainframe back in the 1970s that actually did that. Univac 1108 or 1100, maybe? Maybe only in some particular mode?

Re:The x86 architecture is the weirdo, part 2 by notacoward on Friday April 22, 2022 @08:26PM (#31129993)
I once worked on the MC88K which had this behavior at the instruction level, and I think other contemporary RISC processors did as well. Never saw it in a higher-level language, though. Maybe some variant of SNOBOL (which already had success/failure branches for every line)?