News for hackers. Stuff that matters.
Re:Verilog Is Weird by phkahler on Wednesday March 23, 2022 @10:01AM (#30778538)
>> always @(posedge clk)

Is there an option for bothedge clk?

Re:Verilog Is Weird by nrclark on Wednesday March 23, 2022 @11:38AM (#30779584)
It's not synthesizable, but you could say "always @(clk)" as well.
Re:Verilog Is Weird by sguav on Wednesday March 23, 2022 @10:07AM (#30778592)
always @(posedge clk or negedge clk)
Re:Verilog Is Weird by acadiasprings on Wednesday March 23, 2022 @10:16AM (#30778681)
This is the correct syntax, though many FPGA architectures don't support double edge registers
Re:Verilog Is Weird by sguav on Wednesday March 23, 2022 @10:46AM (#30778973)
True, I directly answered the syntax-related question, but talking about implementation this would be a bad description - be it FPGA or ASIC.

As the parent's-parent comment said in other words, think circuit first.