Re:Verilog Is Weird
by acadiasprings on Wednesday March 23, 2022 @10:16AM
(#30778681)
This is the correct syntax, though many FPGA architectures don't support double edge registers
[ Parent
| on HN ]
True, I directly answered the syntax-related question, but talking about implementation this would be a bad description - be it FPGA or ASIC.
As the parent's-parent comment said in other words, think circuit first.