Re:SiFive Tapes Out First 5nm TSMC 32-bit RISC-V Chip with 7...
by foobiekr on Friday April 16, 2021 @01:41PM
(#26836908)
While these are all good points, this really does not appear to be a competitive NPU design on any axis that matters. I don’t know what this chip is for, but a router NPU it is not, nor a switch. Maybe some soho switch or smart NIC, but those have moved on far along the performance spectrum away from the place where this would fit.
Re:SiFive Tapes Out First 5nm TSMC 32-bit RISC-V Chip with 7...
by rjsw on Friday April 16, 2021 @01:09PM
(#26836521)
Routers need quite a bit of memory to handle IPv6.
Switches as an application of this makes sense.
Re:SiFive Tapes Out First 5nm TSMC 32-bit RISC-V Chip with 7...
by jandrese on Friday April 16, 2021 @05:18PM
(#26839190)
IPv6 address comparison on a 32 bit design is fairly awkward. Switches won't care, but routers need to make routing decisions.
Re:SiFive Tapes Out First 5nm TSMC 32-bit RISC-V Chip with 7...
by GoblinSlayer on Friday April 16, 2021 @03:44PM
(#26838286)
It's E76 with F set, and F set is huge compared to RV64I. And the article proposes HPC as possible application.
* HBM3 for the highest memory bandwidth (10Gbps switches need tons and tons of bandwidth. That's 10Gbps per direction per connection, 8x ports is 160Gbps, and then that's multiplied multiple times over by every memcpy / operation your chip actually does. You need to DELIVER 160Gbps, which means your physical RAM-bandwidth needs to be an order of magnitude greater than that)
* Embedded 32-bit design for low-power usage.
* All switches have small, fixed size buffers. Memory capacity is not a problem, its feasible to imagine useful switches and routers (even 10Gbps, 40Gbps, or 100Gbps) that only have hundreds-of-MBs of RAM. As such, 32-bit is sufficient and 64-bit is a waste (You'd rather half your pointer memory requirements with 32-bit pointers rather than go beyond 4GB capacity)