Routers / Switches have extremely weird performance characteristics, and I think that's what SiFive is targeting with this chip.

* HBM3 for the highest memory bandwidth (10Gbps switches need tons and tons of bandwidth. That's 10Gbps per direction per connection, 8x ports is 160Gbps, and then that's multiplied multiple times over by every memcpy / operation your chip actually does. You need to DELIVER 160Gbps, which means your physical RAM-bandwidth needs to be an order of magnitude greater than that)

* Embedded 32-bit design for low-power usage.

* All switches have small, fixed size buffers. Memory capacity is not a problem, its feasible to imagine useful switches and routers (even 10Gbps, 40Gbps, or 100Gbps) that only have hundreds-of-MBs of RAM. As such, 32-bit is sufficient and 64-bit is a waste (You'd rather half your pointer memory requirements with 32-bit pointers rather than go beyond 4GB capacity)

While these are all good points, this really does not appear to be a competitive NPU design on any axis that matters. I don’t know what this chip is for, but a router NPU it is not, nor a switch. Maybe some soho switch or smart NIC, but those have moved on far along the performance spectrum away from the place where this would fit.

Routers need quite a bit of memory to handle IPv6.

Switches as an application of this makes sense.

IPv6 address comparison on a 32 bit design is fairly awkward. Switches won't care, but routers need to make routing decisions.

It's E76 with F set, and F set is huge compared to RV64I. And the article proposes HPC as possible application.

The core is supposed to compete with the Cortex M7. The smallest process M7 I can find is the STM32H7, which is 40nm.

I rave for stm32 with high end processes (10nm or less), whether that makes sense or not. I just love stm32..

With my industry / product management / business strategy hat on, totally agree from SiFive's perspective.

With my early days electronics hat on, the 5nm process adds additional energy performance gains that in conjunction with RISCV in an embedded environment, especially in a battery powered remote operation use case, has me salivating at what could be achieved from a would-be customer perspective.

I think it means 32 bit floating point, not 32 bit CPU, as it mentions "other relatively simplistic applications that do not require full precision" but its a bit unclear.

The quote that stands out to me is that the core is "ideal for applications which require high performance -- but have power constraints (e.g., Augmented Reality and Virtual Reality , IoT Edge Compute, Biometric Signal Processing, and Industrial Automation)."

Yeah, this seems like an odd move to me.

For this kinda of applications the static leakage of the newer & smaller node will probably hurt rather than help.