Re:AMD Patent Reveals Hybrid CPU-FPGA Design That Could Be E...
by mhh__ on Sunday January 03, 2021 @06:48PM
(#25626432)
On paper at least it could be good idea for a company in lattice's position, at very least academics would probably switch.
I would like to see a FAANG try and support some open tools - it doesn't have to be anything legally sketchy like reverse engineering bitstreams - for example, Yosys only has limited SystemVerilog support
Re:AMD Patent Reveals Hybrid CPU-FPGA Design That Could Be E...
by WideCharr on Sunday January 03, 2021 @09:58PM
(#25627519)
Going to plug my work on this here: https://github.com/MikePopoloski/slang
At some point I'd like to see it integrated as the frontend to tools like Yosys to get best-in-class SystemVerilog support in open tools.
Lattice is seemingly at "wink wink, nudge nudge" levels of support -- their lawyers won't allow them to say anything because they're afraid of pissing off Synopsys, but they also know that they're currently the best supported platform, and don't seem interested in deliberately making things difficult.