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Re:AMD Patent Reveals Hybrid CPU-FPGA Design That Could Be E... by mhh__ on Sunday January 03, 2021 @06:48PM (#25626432)
On paper at least it could be good idea for a company in lattice's position, at very least academics would probably switch.

I would like to see a FAANG try and support some open tools - it doesn't have to be anything legally sketchy like reverse engineering bitstreams - for example, Yosys only has limited SystemVerilog support

Re:AMD Patent Reveals Hybrid CPU-FPGA Design That Could Be E... by WideCharr on Sunday January 03, 2021 @09:58PM (#25627519)
Going to plug my work on this here: https://github.com/MikePopoloski/slang

At some point I'd like to see it integrated as the frontend to tools like Yosys to get best-in-class SystemVerilog support in open tools.

Re:AMD Patent Reveals Hybrid CPU-FPGA Design That Could Be E... by mhh__ on Sunday January 03, 2021 @10:19PM (#25627619)
Good luck