Re:AMD Patent Reveals Hybrid CPU-FPGA Design That Could Be E...
by WideCharr on Sunday January 03, 2021 @09:58PM
(#25627519)
Going to plug my work on this here: https://github.com/MikePopoloski/slang
At some point I'd like to see it integrated as the frontend to tools like Yosys to get best-in-class SystemVerilog support in open tools.
I would like to see a FAANG try and support some open tools - it doesn't have to be anything legally sketchy like reverse engineering bitstreams - for example, Yosys only has limited SystemVerilog support