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A comment on AMD Patent Reveals Hybrid CPU-FPGA Design That Could Be Enabled by Xilinx Tech. Parent comment
At some point I'd like to see it integrated as the frontend to tools like Yosys to get best-in-class SystemVerilog support in open tools.
At some point I'd like to see it integrated as the frontend to tools like Yosys to get best-in-class SystemVerilog support in open tools.