MIT 6.004 L14: Implementing RISC-V Processor in Hardware

Re:MIT 6.004 L14: Implementing RISC-V Processor in Hardware by egsmi on Saturday November 28, 2020 @12:54PM (#25239095)

For me probably the coolest thing about RISC-V is it has version with a simple enough architecture that students can code it in a quarter, and it's also in the zeitgeist in a way MIPS never was. It seems like we've been doing toy MIPS implementations for years [1] but they just never captured the imagination in the same way. RISC-V feels almost like the cpu architect's MINIX. :)

[1] Just one random example http://pages.hmc.edu/harris/cmosvlsi/4e/index.html

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Re:MIT 6.004 L14: Implementing RISC-V Processor in Hardware by Cojen on Saturday November 28, 2020 @04:01PM (#25240509)

I guess it all depends on what side you're coming from. When I was in school, I studied MIPS from the perspective of a compiler writer who's only casually interested in hardware design. Having learned a couple of CISC designs beforehand, I found MIPS to be absolutely genius in comparison. I wasn't interested so much in implementing a MIPS processor, just coding for it.

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Re:MIT 6.004 L14: Implementing RISC-V Processor in Hardware by carapace on Saturday November 28, 2020 @03:57PM (#25240477)

Probably a sanguine moment to mention that the selfie project appears to have migrated from MIPS to RISC-V:

https://selfie.cs.uni-salzburg.at/

> An educational software system of a tiny self-compiling C compiler, a tiny self-executing RISC-V emulator, and a tiny self-hosting RISC-V hypervisor.

> Selfie is a project of the Computational Systems Group at the Department of Computer Sciences of the University of Salzburg in Austria.

> The Selfie Project provides an educational platform for teaching undergraduate and graduate students the design and implementation of programming languages and runtime systems. The focus is on the construction of compilers, libraries, operating systems, and even virtual machine monitors. The common theme is to identify and resolve self-reference in systems code which is seen as the key challenge when teaching systems engineering, hence the name.

(No affiliation, I just like it.)

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Re:MIT 6.004 L14: Implementing RISC-V Processor in Hardware by bogomipz on Sunday November 29, 2020 @12:17PM (#25246440)

Wow this is a very cool project! Do you know of any available video lecture from anyone teaching the curriculum? Unfortunately the name of the project makes searching a little difficult.

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Re:MIT 6.004 L14: Implementing RISC-V Processor in Hardware by carapace on Sunday November 29, 2020 @07:53PM (#25249668)

Cheers! I know what you mean about the name. I don't know of any videos offhand but you could just drop them an email and ask?

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Re:MIT 6.004 L14: Implementing RISC-V Processor in Hardware by bogomipz on Saturday November 28, 2020 @02:08PM (#25239672)

>"For me probably the coolest thing about RISC-V is it has version with a simple enough architecture that students can code it in a quarter"

What do you mean by "version" here? How does it add to its accessibility?

I'm curious about your or anyone else's opinion of that "CMSO VLSI Design" text book you linked to. It's quite expensive and I haven't been able to bring myself to buy it. Would you recommend it?

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Re:MIT 6.004 L14: Implementing RISC-V Processor in Hardware by egsmi on Saturday November 28, 2020 @02:18PM (#25239739)

This class’s version of RISC-V only implements of subset of all the possible instructions (which of course is totally appropriate) and it’s missing modern concepts (like out of order execution) which are also out of scope for an introductory class. One of the lectures describes basic logic gates so one doesn’t go from that to reorder buffers in a single quarter.

I think the Weste text book is an excellent introduction to the reality of (mostly) modern digital VLSI design. My only gripe is it’s weak on analog, which is my forte. For An introduction to the reality of that I think Baker’s text at cmosedu.com is better.

Basically, if you have interest in the subject buying a used copy of Weste is not likely to disappoint. Or perhaps see if your local library can snag a copy before you buy.

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Re:MIT 6.004 L14: Implementing RISC-V Processor in Hardware by bogomipz on Saturday November 28, 2020 @03:42PM (#25240366)

Oh I see. Yes it's a modular design. That's one of the most fascinating elements of the CPU. I wasn't familiar with the version terminology to denote features. Thanks. Also thank for the the feedback on the Weste book. I will try to find a used copy.

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Re:MIT 6.004 L14: Implementing RISC-V Processor in Hardware by egsmi on Wednesday December 09, 2020 @02:36PM (#25363378)

> familiar with the version terminology

That's probably because I was using the wrong word. I should've said "variant".

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Re:MIT 6.004 L14: Implementing RISC-V Processor in Hardware by the_duke on Saturday November 28, 2020 @02:20PM (#25239758)

> What do you mean by "version" here? How does it add to its accessibility?

The base variant of RISC-V (RV32/64I) is extremely bare bones.

Even instructions for integer multiplication/division and floating points, atomics, ... are all added by extensions.

See https://en.wikichip.org/wiki/risc-v/standard_extensions

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Re:MIT 6.004 L14: Implementing RISC-V Processor in Hardware by nickik on Saturday November 28, 2020 @03:03PM (#25240070)

Because MIPS was proprietary and it could never be more then a toy.

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Re:MIT 6.004 L14: Implementing RISC-V Processor in Hardware by swiley on Saturday November 28, 2020 @06:28PM (#25241478)

IIRC MIPS 4000 had source available and could be used freely.

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