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A comment on MIT 6.004 L14: Implementing RISC-V Processor in Hardware. Parent comment
The base variant of RISC-V (RV32/64I) is extremely bare bones.
Even instructions for integer multiplication/division and floating points, atomics, ... are all added by extensions.
See https://en.wikichip.org/wiki/risc-v/standard_extensions
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The base variant of RISC-V (RV32/64I) is extremely bare bones.
Even instructions for integer multiplication/division and floating points, atomics, ... are all added by extensions.
See https://en.wikichip.org/wiki/risc-v/standard_extensions