Amazon RDS on Graviton2 Processors

Re:Amazon RDS on Graviton2 Processors by _msw_ on Thursday October 22, 2020 @04:59PM (#24863232)

  [ec2-user@ip-10-0-42-228 ~]$ lscpu
  ...
  L1d cache:           64K
  L1i cache:           64K
  L2 cache:            1024K
  L3 cache:            32768K

Find a deep dive on the cache and memory micro-architecture here: https://www.anandtech.com/show/15578/cloud-clash-amazon-grav...

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Re:Amazon RDS on Graviton2 Processors by wyldfire on Thursday October 22, 2020 @05:52PM (#24863701)

Of course, you can't compare those directly with epyc/xeon because of the architectural/instruction set differences.

EDIT: meaning that a larger sized cache wouldn't necessarily deliver better performance (though I think in this case the architectural differences do favor Graviton making better use of cache)

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Re:Amazon RDS on Graviton2 Processors by darksaints on Thursday October 22, 2020 @07:58PM (#24864671)

I couldn't find anything on the differences between the two different L1 caches. What's the purpose for a second L1 cache?

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Re:Amazon RDS on Graviton2 Processors by sitharus on Thursday October 22, 2020 @08:05PM (#24864725)

The ARM architecture is a modified Harvard architecture, so the CPU has separate instruction and data L1 caches. x86 CPUs don't have this separation.

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Re:Amazon RDS on Graviton2 Processors by lights0123 on Thursday October 22, 2020 @08:21PM (#24864849)

  $ lscpu
  Architecture:                    x86_64
  Model name:                      AMD Ryzen 7 2700X Eight-Core Processor
  L1d cache:                       256 KiB
  L1i cache:                       512 KiB
  L2 cache:                        4 MiB
  L3 cache:                        16 MiB

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Re:Amazon RDS on Graviton2 Processors by senkora on Thursday October 22, 2020 @08:17PM (#24864817)

I’m pretty sure x86 does have split L1i and L1d.

From Wikipedia (not the best source I know):

“L1 cache size unchanged at 32 KB (KiB) instruction and 32 KB (KiB) data cache per core.“

https://en.m.wikipedia.org/wiki/Skylake_(microarchitecture)

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