Re:Amazon RDS on Graviton2 Processors
by lend000 on Thursday October 22, 2020 @04:43PM
(#24863095)
How big are the L1 and L2 caches? I couldn't find it in the article.
[ Parent
| on HN ]
[ec2-user@ip-10-0-42-228 ~]$ lscpu
...
L1d cache: 64K
L1i cache: 64K
L2 cache: 1024K
L3 cache: 32768K
Of course, you can't compare those directly with epyc/xeon because of the architectural/instruction set differences.
EDIT: meaning that a larger sized cache wouldn't necessarily deliver better performance (though I think in this case the architectural differences do favor Graviton making better use of cache)
Re:Amazon RDS on Graviton2 Processors
by darksaints on Thursday October 22, 2020 @07:58PM
(#24864671)
I couldn't find anything on the differences between the two different L1 caches. What's the purpose for a second L1 cache?
The ARM architecture is a modified Harvard architecture, so the CPU has separate instruction and data L1 caches. x86 CPUs don't have this separation.
Re:Amazon RDS on Graviton2 Processors
by lights0123 on Thursday October 22, 2020 @08:21PM
(#24864849)
$ lscpu
Architecture: x86_64
Model name: AMD Ryzen 7 2700X Eight-Core Processor
L1d cache: 256 KiB
L1i cache: 512 KiB
L2 cache: 4 MiB
L3 cache: 16 MiBI’m pretty sure x86 does have split L1i and L1d.
From Wikipedia (not the best source I know):
“L1 cache size unchanged at 32 KB (KiB) instruction and 32 KB (KiB) data cache per core.“