MIPS is sort of the original RISC, since one of the two originators of the RISC concept (Hennessy) was a founder of MIPS Computer Systems in 1984. POWER is also RISC, but basically doesn't have any traction beyond IBM itself. SPARC lives on only in radiation-hardened form for the European space agency. Various others never even achieved that level of commercial significance. So it's basically "less RISC than it used to be" Arm, and "more RISC than it used to be" x86.

But there is one notable CISC still out there: IBM's mainframe z/Architecture. Might not sell a lot of units, but it's still pretty important commercially.

> SPARC lives on only in radiation-hardened form for the European space agency.

Worth noting that POWER similarly lives on in radiation-hardened form for NASA; the RAD750 (and its predecessor, the RAD3000) both have a long history of interplanetary use.

MIPS also sees some use here, too; for example, the MIPS-based Mongoose-V is what New Horizons uses, and the KOMDIV-32 ostensibly is designed for Russian spacecraft use (but I don't know of any specific examples).

MIPS itself is a RISC, see https://en.wikipedia.org/wiki/MIPS_architecture

As for what else is out there in large numbers, I think a lot of 8bit Z80 and AVR microcontrollers (like the ATmega328 used in Arduino Uno) are embedded in larger systems and go unnoticed. More recently I've seen the Xtensa (32bit RISC) catching on with the popular ESP32 and ESP8266 SOCs.

A number of others you might encounter in your embedded devices: 68k, AVR, Z80. (CISC, RISC, CISC, if you’re curious.)

There’s (sadly) not that much 68k left these days, is there? Do you know of any specific companies still using them? (maybe ones that are hiring? :)

AST2500 (popular as BMC chip) has ColdFire coprocessor, TALOS2 and Blackbird (truly open source POWER9 workstations) use it (used?) to bit bang one of the protocols necessary to start up the CPUs

I wrote a lot of code for it 12 years ago in embedded programming. It was already getting less popular back then so I guess you're right. Haven't seen one in forever.

I think either Airbus or Boeing (or both?) use them in some of their planes (A320 and/or 737)

In terms of hardware: NXP ColdFire.

The Apollo Vampire is a newly-designed implementation on FPGA's that compares very favorably wrt. performance with existing 68k (and ColdFire) hardware.

I assume that all modern CPUs are CISC-ish opcodes running in microcode on a RISC-ish core, and it’s been a few decades since those were useful labels.

There's nothing much that's CISC-like about ARM, MIPS or RISC-V. Even many μC architectures are closer to "RISC" than "CISC", though there's at least some room for exceptions there.

> There's nothing much that's CISC-like about ARM,

I struggle to think that ARM can really be called reduced-instruction after neon or so.

RISC has never been about reduced number of instructions, but their complexity. A SIMD extension built around load/store architecture is quite compatible with the principles of RISC, despite the fact that such an extension might have very numerous instructions.

Well, I learned something today:) I'd always assumed that RISC meant a reduced number of instructions, but that's clearly not the case. Wikipedia phrases it as,

> The term "reduced" in that phrase was intended to describe the fact that the amount of work any single instruction accomplishes is reduced—at most a single data memory cycle—compared to the "complex instructions" of CISC CPUs that may require dozens of data memory cycles in order to execute a single instruction.[23] In particular, RISC processors typically have separate instructions for I/O and data processing.

So yeah, if SIMD instructions can execute in a single cycle (or maybe even a small number), then it still counts.

Why? NEON operates on registers, so the load-store principle is still fully in effect. And it maps directly to special-purpose hardware.

32-bit Arm has some features that make it less RISC-like than others:

- Predication as a major architectural feature -- every instruction can be conditionally executed - Complex load-store instructions: ldm/stm can operate on a large set of registers in a single instruction, including performing a branch by loading into the instruction pointer - 16-bit Thumb instruction format (also optionally present in RISC-V and newer MIPS)

64-bit Arm mostly drops all of the above and is basically a traditional RISC implementation.

RISCs still largely operate on the architected instructions in the pipelines.

It's also a thing to fuse smaller operations into macro-ops in many microarchitectures.

All high performance chips avoid running microcode, it's reserved for eg emulating seldom used legacy instructions. Microcoded CPUs (where all instuctions are implemented with microcode) were a 80s/90s thing.

They're all RISC.