RISC has never been about reduced number of instructions, but their complexity. A SIMD extension built around load/store architecture is quite compatible with the principles of RISC, despite the fact that such an extension might have very numerous instructions.

Well, I learned something today:) I'd always assumed that RISC meant a reduced number of instructions, but that's clearly not the case. Wikipedia phrases it as,

> The term "reduced" in that phrase was intended to describe the fact that the amount of work any single instruction accomplishes is reduced—at most a single data memory cycle—compared to the "complex instructions" of CISC CPUs that may require dozens of data memory cycles in order to execute a single instruction.[23] In particular, RISC processors typically have separate instructions for I/O and data processing.

So yeah, if SIMD instructions can execute in a single cycle (or maybe even a small number), then it still counts.

Why? NEON operates on registers, so the load-store principle is still fully in effect. And it maps directly to special-purpose hardware.

32-bit Arm has some features that make it less RISC-like than others:

- Predication as a major architectural feature -- every instruction can be conditionally executed - Complex load-store instructions: ldm/stm can operate on a large set of registers in a single instruction, including performing a branch by loading into the instruction pointer - 16-bit Thumb instruction format (also optionally present in RISC-V and newer MIPS)

64-bit Arm mostly drops all of the above and is basically a traditional RISC implementation.