Well, I learned something today:) I'd always assumed that RISC meant a reduced number of instructions, but that's clearly not the case. Wikipedia phrases it as,

> The term "reduced" in that phrase was intended to describe the fact that the amount of work any single instruction accomplishes is reduced—at most a single data memory cycle—compared to the "complex instructions" of CISC CPUs that may require dozens of data memory cycles in order to execute a single instruction.[23] In particular, RISC processors typically have separate instructions for I/O and data processing.

So yeah, if SIMD instructions can execute in a single cycle (or maybe even a small number), then it still counts.