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Re:5/3nm Wars Begin by rwmj on Saturday January 25, 2020 @01:20PM (#22147680)
Smaller transistors use less power, it's not always about increasing speed. Your smartphone, if it's anything like mine, would be better if it had a longer running time between charges.

Having said that, the very first users will be high end servers. It's no accident that IBM were the first to demonstrate 5nm wafers a few years ago[1], because they'll use them in their top of the line POWER chips. Those chips have incredible single thread performance, but also incredible prices (and apparently very low yields). If you're the sort of person who wonders who would pay money for that, then you're not the target customer :-) (Disclosure: I now work indirectly for IBM)

[1] https://www.ibm.com/blogs/think/2017/06/5-nanometer-transist...

Re:5/3nm Wars Begin by blp on Saturday January 25, 2020 @03:45PM (#22148516)
This is just....not true. IBM doesn’t make 5nm chips. This is a research demo of a transistor design for that node. They don’t make it, and never will.
Re:5/3nm Wars Begin by hindsightbias on Saturday January 25, 2020 @01:38PM (#22147785)
Power has never been on the latest node, and Global Foundaries abandoned that node over a year ago. POWER10 will by all accounts be a Samsung node
Re:5/3nm Wars Begin by Fronzie on Saturday January 25, 2020 @02:50PM (#22148242)
> Smaller transistors use less power.

Don't the smaller transistors also have higher leakage? I thought that below 10nm scaling down further would not give power benefits.

Re:5/3nm Wars Begin by unlinked_dll on Saturday January 25, 2020 @03:06PM (#22148336)
It's called Dennard Scaling [0] and it ran out about 15 years ago

[0] https://en.wikipedia.org/wiki/Dennard_scaling

Re:5/3nm Wars Begin by Dylan16807 on Saturday January 25, 2020 @05:48PM (#22149119)
Having constant power density with continuous performance improvements broke down.

But we're not yet at the point where power density increases as fast as transistor density.

Re:5/3nm Wars Begin by chas on Saturday January 25, 2020 @07:08PM (#22149480)
While this is true for many process nodes, it is not true in general. For instance, the transition to FinFETs greatly reduced leakage power in TSMC 16nm in comparison to their 28nm processes.
Re:5/3nm Wars Begin by 1123581321 on Saturday January 25, 2020 @02:10PM (#22147987)
For mobile, increased power efficiency is speed as it allows heavier COU usage with the same battery life.
Re:5/3nm Wars Begin by ebg13 on Saturday January 25, 2020 @05:42PM (#22149079)
> Your smartphone, if it's anything like mine, would be better if it had a longer running time between charges

Little of your phone battery goes to the CPU. It's almost all screen and radios.

Re:5/3nm Wars Begin by Kirby64 on Saturday January 25, 2020 @06:07PM (#22149214)
That's just not true. Although screens and radios definitely suck a lot of power, having the CPU handle traffic from all the connectivity better translates to better battery (especially in standby states). Also, the modems are usually built into the main SoC (i.e. CPU) these days, so node decreases translates to a more efficient baseband modem too.