Smaller transistors use less power, it's not always about increasing speed. Your smartphone, if it's anything like mine, would be better if it had a longer running time between charges.

Having said that, the very first users will be high end servers. It's no accident that IBM were the first to demonstrate 5nm wafers a few years ago[1], because they'll use them in their top of the line POWER chips. Those chips have incredible single thread performance, but also incredible prices (and apparently very low yields). If you're the sort of person who wonders who would pay money for that, then you're not the target customer :-) (Disclosure: I now work indirectly for IBM)

[1] https://www.ibm.com/blogs/think/2017/06/5-nanometer-transist...

This is just....not true. IBM doesn’t make 5nm chips. This is a research demo of a transistor design for that node. They don’t make it, and never will.

Power has never been on the latest node, and Global Foundaries abandoned that node over a year ago. POWER10 will by all accounts be a Samsung node

> Smaller transistors use less power.

Don't the smaller transistors also have higher leakage? I thought that below 10nm scaling down further would not give power benefits.

It's called Dennard Scaling [0] and it ran out about 15 years ago

[0] https://en.wikipedia.org/wiki/Dennard_scaling

Having constant power density with continuous performance improvements broke down.

But we're not yet at the point where power density increases as fast as transistor density.

While this is true for many process nodes, it is not true in general. For instance, the transition to FinFETs greatly reduced leakage power in TSMC 16nm in comparison to their 28nm processes.

For mobile, increased power efficiency is speed as it allows heavier COU usage with the same battery life.

> Your smartphone, if it's anything like mine, would be better if it had a longer running time between charges

Little of your phone battery goes to the CPU. It's almost all screen and radios.

That's just not true. Although screens and radios definitely suck a lot of power, having the CPU handle traffic from all the connectivity better translates to better battery (especially in standby states). Also, the modems are usually built into the main SoC (i.e. CPU) these days, so node decreases translates to a more efficient baseband modem too.

“It’s safe to say that not all need advanced nodes. But Apple, HiSilicon, Intel, Samsung and Qualcomm require advanced technologies, and for good reason.”

“The design cost for a 3nm chip is $650 million, compared to $436.3 million for a 5nm device, and $222.3 million for 7nm, according to IBS. These are “mainstream design costs,” which means one year after a given technology has moved into production.”

The new nodes will only be used where the design costs can be recovered, which is mostly consumer and server farms AFAIK. Basically anything using the current best nodes will use the next gen nodes.

Probably FPGAs. They're commonly used to refine foundary processes because of how regular their layouts are. Also, the smaller the gates on your FPGA, the more logic blocks you can pack on it.

Top-end networking equipment e.g. routers, 5g stuff.

Also, graphics cards, server processors, and possibly now also automotive stuff.

Intel tends to push new technology into laptop chips first while AMD does the opposite. This is merely a business decision on the part of AMD to play to their strengths.

Right now you can get a 10nm Intel part in a laptop but not for the desktop.

Intel’s 10nm is laptop first. It’s easier to yield smaller chips

Exactly. And when it comes to tuning/fixing your process with small, easy chips at large volumes, Intel have only really got laptop devices to play with at 10nm. TSMC and Samsung did this with SoCs.