Fast buses operate at some multiple of a reference clock wired up to both sides, it's often 1/2 or 1/8th of the actual data rate which each side arrives at by feeding the reference clock to an on-die pll.

This can create ambiguity in which bit of the 2 or 8 or whatever is on the bus, and temperature, board design, bus length, humidity etc change the phase where the best sampling place is for the data signal. So there is 'training' to test which fine delay between the receiver pll clock and the data gives the lowest error rate when used to sample the incoming data. Periodically some buses must pause and do retraining to account for, eg, temperature changes.

That seems so awfully analogue... :-/

It is... underneath all that shiny logical digital it's analogue all the way down in any real implementation.

Pace Fredkin.

It's hardware:) At that level, "digital" electronics... aren't.

Modern DDR PHYs require PLL training and adjustment to communicate to the RAM chips because DDR is runs at such high speeds that it is mostly operating in the analog domain these days.

Often this is done by setting registers. The trick is that its hundreds of thousands of registers to alter the way the PHY behaves with regard to impedance and other parameters, and the vast majority are undocumented. So its done with a two stage thing: the first is a generative program that analyses the eye diagrams using feedback from the PHY over a long period of time to get the majority of the settings.

The second half is actually getting the PHY PLLs to sync with the clocks and the RAM, which is done by the PHY at runtime, every boot.

Good article: https://blog.asset-intertech.com/test_data_out/2014/11/memor...

Basically it's the memory chip bring up procedure of the memory controller. It figures out what kind of ram is on the bus, configures and even tests it so it's ready for use.

It seems that memory is “trained” on boot — the system does POST and checks that critical hardware is responding as expected. PC motherboards have some settings to adjust timing for enthusiasts, but I’m not sure that that’s a trend or even desirable in consumer electronics. So these expected values are probably “burnt in” to the design and difficult to change.

Maybe Purism has a way to do this?

I am not an expert!

The memory isnt trained -- the PHY is. Its PLL and signal adjustment -- not too dissimilar to how a cable modem "trains" to get settings right for your specific line's characteristics.

PCs have codified it mostly to a set of well known and understood timings that are interchangable, so in that domain its easy. But raw DDR chips used with SOCs is much much harder because you're not beholden to Intel's standards for the PHY or the RAM.