The billion cores mark for RISC-V will be somewhere around the middle of 2020 thanks to Western Digital and Microsemi.
https://www.forbes.com/sites/tiriasresearch/2017/12/06/weste...
> What many do not realize is that the company ships over 1 billion processor cores within its products each year and is moving toward 2 billion per year.
https://hackaday.com/2019/02/13/western-digital-releases-the...
> Last year, Western Digital made the amazing claim that they will transition their consumption of silicon over to RISC-V, putting one Billion RISC-V cores per year into the marketplace.
https://www.microsemi.com/product-directory/mi-v-embedded-ec...
RISC-V doesn't have historical warts only because it's too new for any warts it has to be considered historical.
> that can slow down not just hardware implementations but emulation
RISC-V shuffles the immediate bits on its instruction encoding to speed up decoding the immediate in hardware, but this slows down decoding the immediate in software. This will in the future probably be considered one of RISC-V's "historical warts".
You're right that this might be a problem, in principle. Surprisingly enough, however, RV is actually more than competitive as a system-level virtual ISA. People have experimented with this on existing emulation platforms, and that was the result they got.