> RISC-V shuffles the immediate bits on its instruction encoding to speed up decoding the immediate in hardware
You're right that this might be a problem, in principle. Surprisingly enough, however, RV is actually more than competitive as a system-level virtual ISA. People have experimented with this on existing emulation platforms, and that was the result they got.
RISC-V doesn't have historical warts only because it's too new for any warts it has to be considered historical.
> that can slow down not just hardware implementations but emulation
RISC-V shuffles the immediate bits on its instruction encoding to speed up decoding the immediate in hardware, but this slows down decoding the immediate in software. This will in the future probably be considered one of RISC-V's "historical warts".