Doesn't matter, as explained in the second paragraph of the article: the air gap (35 nm) is shorter than the mean free path [1] in air, so the electrons are effectively moving in a vacuum.
> Is this basically the return of the thermionic valve after fifty years in the wilderness?
Yes. The paper's abstract starts out saying just that: "Scattering-free transport in vacuum tubes has always been superior to solid-state transistors. It is the advanced fabrication with mass production capability at low cost which drove solid-state nanoelectronics. Here, we combine the best of vacuum tubes with advanced nanofabrication technology." [2]
That’s true enough for a single cycle of a single transistor, not so much a billion of them doing a billion operations per second. Which is why they are calling this “vacuum-like.”
They generally aren't. Vacuum as-in the medium may be technically superior, but vacuum tubes as practically implemented weren't just displaced because solid state was easier to manufacture, but also because solid state quickly outperformed valves in many areas. (There are areas where valves held out for much longer and are still used today in some cases, e.g. transmitter output stages).
That being said a great thing about valves is that they're very hard to kill. They can take huge momentary overloads (a bit like magnetics, but with much shorter time constants), which would literally detonate similarly specced solid state output stages. And because they can run much hotter than any known solid state tech they can have huge energy densities and can be cooled very efficiently (boiling water cooling): https://upload.wikimedia.org/wikipedia/commons/8/80/Rs2041_s... (Siemens RS2041V, 600 kW output tube, diameter of the copper anode dissipating about 240 kW is 239 mm, was still made in 1999)
Well, it's not even clear why they think it helps a 3D architecture. AFAIK, there is no mature layer deposition technique that allows gaps for the vacuum those transistors require, so I'd imagine it makes 3D harder.
For cooling, keep in mind that at those scales air cooling is much less efficient than conductive cooling.
> Does this mean that chips would have less resistive heating?
Complementary logic (the "C" in C-MOS) sets the heat dissipation into a fixed amount per clock cycle, whatever resistance you have. When you hear about "lower resistance transistors", you should hear "higher frequency transistors".
> is there is also a lattice-spacing constraint
There is also a lattice-spacing constraint. Manufacture constraints don't change (they used a well known, very expensive, and hard to scale technique for their proof of concept), insulation constraints don't go away, and they replaced the charge carrier orbital constraints with a constraint on the length of the electrode separation.
You can make electrons jump from emitter to collector over nanoscopic distances in "air," but how to you make a hole to do the same? With my level of understanding of physics, that's impossible.
And without a P device, you can't make a CMOS pair. Thus, any logic family using it will eat tons of current.
You can't use it for logic in a real world application, but if they can solve the endurance issue, that will be an enviable device for use in power gating. Active logic may also be of interest (it is still being used for ultra high frequency DACs in military radar tech)
Unlike semiconductor devices, there is only one "kind" of vacuum tube. A push-pull amplifier with vacuum tubes requires an anti phase generator before the high and low side drivers, while with both n- and p- type available you sorta get this for free.
No. The parts of the chip that conduct electricity to the active areas in current chips are already made from metal. Basic chips are made from layers of metal / oxide / semiconductor (MOS).
Current flows through silicon only in small areas, and the way chips work is that you can "turn off" the high resistivity in those areas and make them conducting (by doping the material + applying electric currents & fields)
In the presented work, an air gap is used for these "active areas" instead of a semiconductor. An air gap does have resistance, so there will be resistive heating just like in normal chips.
In CMOS, only one device of a PMOS/NMOS pair is open at the time. In simplest terms: electric field gets through a CMOS device, but not so much of current.
They also mentioned putting these in a vacuum. Presumably that won't have as much resistance as an air gap.
Given a small enough distance, arcing is possible between 2 surfaces in vacuum as charges are ejected from the surface (that’s how vacuum tubes and these transistors work).
Just because EM waves can propagate in vacuum does not mean you can induce a current density.
Obviously you can't induce a current in vacuum, but you can definitely convert EM waves to current flux in a receiving structure.
> Obviously you can't induce a current in vacuum ...
Yes. I wrote that second part because 'mmmBacon seemed to be arguing that one could induce a current in vacuum; that because vacuum has a characteristic impedance, it isn't an insulator (i.e. can support current because it has characteristic impedance).
Diamond is almost perfect though, at 20 gigavolts per metre, and that only given if the diamond has at least some microscopic imperfections.
If that were true, vacuum tubes (used for radio and early computers) wouldn't work.
The key to the function is the heating of the cathode filament. Vacuum tube designs that use a separate heating current (which is, today, most of them) do not conduct if the heating current is not applied. "Cold cathode" type tubes are not vacuum tubes-- they are typically filled with a low-pressure gas.
Vacuum: isolator.
Vacuum filled with electrons: not so good isolator.
Yes, but with a twist of quantum.
> The experimental data shows that influential operation mechanism is Fowler–Nordheim tunnelling in tungsten and gold devices, while Schottky emission in platinum device.
The bad grammar makes this hard to understand; is FN-tunneling the influential mechanism or an influential mechanism? With the help of Wikipedia I can parse it as an explanation of how the electrons get out of the metal.
When you apply an electric field, there can be a potential barrier: the electron must "climb" up out of the metal but can then "fall" down the externally applied field [1]. With Schottky emission, electrons jump the barrier using their thermal energy; increasing the field lowers the barrier, enhancing the emission. All this comes from the days of thermionic diodes.
But as the field increases, the barrier also gets narrower. And when it is narrow enough, even low-energy electrons can get out via quantum tunnelling[2]. Apparently, this is called Fowler–Nordheim tunneling.
Now these named effects both have equations attached to them, which predict the amount of electrons emitted under different circumstances. But real devices are complicated, and involve both of the above physical effects, plus others. So what researches have to deal with are measured curves that kind-a-sort-a fit the equations if you squint.
The mangled sentence in the abstract makes me think that they have measured something (perhaps current vs.temperature curves) look a bit like the Schottky prediction in platinum, and a bit like the Fowler-Nordheim prediction in gold and tungsten.
[1]: https://en.wikipedia.org/wiki/Schottky_effect [2]: https://en.wikipedia.org/wiki/Quantum_tunnelling
* Air presumably doesn't mean atmospheric air here, otherwise you're getting a random mix of gases and water vapour inside your nanoscale wizardry - so will these be nitrogen-filled, like binoculars etc?
* What does this mean for cooling, especially in the high-density 3D architectures mentioned? Can you use air flow through the chip to cool it?
* "tungsten, gold, and platinum were evaluated as metals of choice" - compare their resistivities of 5.60e-8, 2.44e-8, and 1.06e-7 ohm-metres respectively to silicon's of 6.4e+2 [1] (i thought tungsten was much higher than that, TIL). Does this mean that chips would have less resistive heating? Is resistive heating a significant part of the TDP of a modern chip?
* "replacing silicon with metal means these ACT devices can be fabricated on any dielectric surface, provided the underlying substrate allows effective modulation of emission current from source to drain with a bottom-gate field" - is there is also a lattice-spacing constraint, where the substrate's spacing has to work with that of the conductor, as i believe there is with silicon chips?
* Is this basically the return of the thermionic valve after fifty years in the wilderness?
[1] https://en.wikipedia.org/wiki/Electrical_resistivity_and_con...