Oracle: https://www.amd.com/en/press-releases/2018-10-23-amd-and-ora...
Azure: https://azure.microsoft.com/en-us/blog/announcing-the-lv2-se...
AWS: https://aws.amazon.com/about-aws/whats-new/2018/11/introduci...
ie => id est => that is
eg => exempli gratia => for example
Providers will begin uptake of AMD again, it just takes time for contracts to roll over and the new hardware to reach production.
https://www.anandtech.com/show/13578/naples-rome-milan-zen-4...
IC: AMD has already committed that Milan, the next generation after Rome, will have the same socket as Rome. Can you make the same commitment with Zen 4 that was shown on the roadmap slides?
MP: We’re certainly committed to that socket continuity through Milan, and we haven’t commented beyond that. Obviously at some point the industry transitions to PCIe 5.0 and DDR5 which will necessitate a socket change.
IC: So one might assume that an intercept might occur with Zen 4?
MP: No comment (!)
1) PCI-E 5 isn't even standardized yet
2) Mass production of DDR5 memory chips might begin ramping up in 2019, but it's unlikely that DDR 5 memory sticks will be readily available on the market until 2020.
3) It takes a really long time to engineer a cpu architecture and bring it to market (generally a year or more for even just a revision of an existing architecture).
4) Adding support for a new memory or PCI-E version requires a new socket and a new chipset, which creates even more work that by definition can't be "done" until things are fully standardized.
AMD are going to support DDR5 and PCI-E 5 eventually... But they want to release a new architecture revision on their current socket and chipset now before it's reasonably possible to do that.
Edit: All this is to say nothing of AMD's commitment to potential partners to keep the underlying socket and chipset the same for a reasonable period of time, which is critical to planning supply chains and upgrade paths for major partnerships.
Memory, sure, you don't want compatibility issues. Why PCIe, when the important lanes are all driven directly off the CPU?
Zen 2 will be the first CPUs supporting 4.0.
Furthermore...
On June 5th, 2018, the PCI SIG released version 0.7 of the PCIe 5.0 specification to its members.
PLDA announced the availability of their XpressRICH5 PCIe 5.0 Controller IP based on draft 0.7 of the PCIe 5.0 specification on the same day
https://www.plda.com/products/xpressrich5
and...
Historically, the earliest adopters of a new PCIe specification generally begin designing with the Draft 0.5 as they can confidently build up their application logic around the new bandwidth definition and often even start developing for any new protocol features. At the Draft 0.5 stage, however, there is still a strong likelihood of changes in the actual PCIe protocol layer implementation, so designers responsible for developing these blocks internally may be more hesitant to begin work than those using interface IP from external sources.
From here: https://en.wikipedia.org/wiki/PCI_Express
AMD had plenty of time to include PCIe 5.0 even in the Draft 0.7 stage which is pretty much the same as final draft/release, but decided not to.
No possible way that could backfire or be impossible
... Just how long do you think it takes to make that kind of design changes? This requires a major change in silicon. It would have had to been done more than a year ago.
If speculative execution is a problem and you need to give each VM its own exclusive cores, great when you can source parts with 64+ cores on them!