It is cheaper to make chip 4 times the size, than doubling the amount of process layers.

The trick is to add 3D features that don't involve making an entirely new device on top of another. This is the case for RAM, MRAM, and flash memory: they share devices in the stack, the only parts that are being scaled vertically are charge/spin carrying parts, but not amplifiers, backend, data lanes, or other devices.

There was a lot of talk about making 3D standard cells (stuff from which normal, non-memory, devices are made of.) The amount of work is immense. Every year there are a dozen cookie cutter PhD work like "3D NAND/XOR/INVERT device that is N percents smaller than before," but it will take years to cover and unify the whole cornucopia of devices in cell libraries. And only once it's done, will major fabs think of switching to that. No fab will try to add much more litho layers just to reduce footprint of only one device or macrocell.

they are already multiple levels. If you are imagining something like a cube, heat dissipation is a big problem there.

I just learned about microfluidics[1] the other day, so now I'm seeing possible applications everywhere. I wonder if this is one such possible application.

[1]https://en.wikipedia.org/wiki/Microfluidics

How about a sphere-ish thing, then?

Or a tube-like cylindrical thing?

You need more surface area not less.

I suppose a long tube might work, but that'd be a weird shape to work with.

the whole idea of a flat linear trace may be a dead end... high frequencies dont propagate very well through the cross sectional area of a conductor...skin effect and antenna effect dictate many of the design constraints regarding width thickness proximity and linear segment length...we may begin to see hollow duct waveguides required to manage propagation of gigahertz even terahertz frequency electron waves if we dont go full out photonic...im hoping to see carbon/ graphene nanotube die production facilities, even if only experimental for the remainder of my lifetime...lets catch the wave and promote to the next level...

Not insurmountable I would gather. Probably just need microscale heat pipes. Then again, I dunno physics well enough to know this won't work.

3d chips exists in storage chips but not yet in CPUs AFAIK.

https://en.wikipedia.org/wiki/3D_XPoint https://en.wikipedia.org/wiki/Flash_memory#Vertical_NAND

(1) How would you make it? Photo masking is an inherently 2D process. That's why 3D chips are stacked wafers.

(2) How the heck would you cool it?

(2) 4D heatsinks.

Just fold the heat into another dimension

You design it ticker at the moments the computer will be using more power, and thinner at the rest of the time.

paraboloid etching

(2) you run it twice as slow, but compensate it with the fact that now you have 2x the amount of devices

And you look at Amdahl's Law and realize that your 3D chip literally can't be better in performance than your 2D one if you do that.

Interesting standpoint. The current issue with very large pipelines, besides the obvious issue of keeping them IO satiated, is the distance in between branchings in code. In other words the degree to which extend you can "flatten" the computation timewise.

Now imagine, thanks to 3D cells, you now magically get double the number of registers. How much efforts do you think you need to spend to double the amount of loops running in parallel?

1) 3d printing uses 2d slices. Hell SLA is a photomask too.

2) I seem to remember IBM was looking at microfluidics for both power and heat distribution, like our blood.

3D printing is additive. Not sure what SLA is?

I would love to see the microfluidics cooling. I wonder what would happen if you reached boiling though--it'd probably explode the chip.

In this context, SLA = Stereolithography