> They cannot compete with GPUs on flops with Xeon, but an embedded FPGA might get them closer.

FPGAs aren't known for their FLOPs though. Sure, the high end ones pack a punch, but compared to GPUs are still extremely expensive.

Altera has hard floating point blocks in their FPGAs, I don't think any other manufacturer does though.

Yeah - the best Stratix 10 can do 9.2 TFLOPs. A GTX 1080 Ti can do 11.3 TFLOPs. Now I can't find any price info on those Stratixes, but given how expensive these FPGAs generally get, I highly doubt it will be anywhere near the $700 for a 1080 (and that's for the entire card!).

I am not saying these things don't have applications, but the "usual" computational workloads are not one of them.

>programmability remains the big problem for FPGAs

I agree because there's added levels of complexity with HDLs that SW doesn't have to deal with. What would be nice is if there was a tool that you could declare your problem (functions) and your constraints (throughput, LUTs available) and it would figure out the memory, ALUs and pipe-lining needed to solve the problem.

That is called high-level synthesis and there are some tools for this available (and I know at least one company who produces a proprietary toolchain - including hardware - for this).

In my experience, high-level synthesis makes things a lot easier for the programmer, but you still have to be aware of very low-level details (and you still can get bitten by abstractions that you don't fully understand).

That company might fruitfully make their system available within a datacenter / "VPS"-type context, eg the way Cloud9 does it. (https://c9.io/, you make a free account, you instantly get a Web based editor connected to a Debian VM)

If their system accepts "mostly ordinary" code in eg C, a fair amount of stuff would probably work with it, so it could scale beyond educational exploration/tinkering, too.

Here is a service I know of: https://reconfigure.io/

I think they did exactly that with Amazon AWS instances (although I have to admit that I don't know the specifics).

Like this?

https://www.mathworks.com/solutions/fpga-design.html

There are plenty of C-to-HDL languages (https://stackoverflow.com/questions/8988629/can-you-program-...) and there's some interesting tidbits about them in this SO link.

Xeon Phi coprocessors are flops competitive with GPUs and are used in many supercomputers.

Embedded FPGA accelerators are of interest primarily to large server farms and cloud operators, where the cost of development for FPGA acceleration is cheaper than the savings of acceleration-- Microsoft in particular has done a lot of work in this area (for Bing), and probably worked with Intel to define the CPU.

Pretty sure that Phi as you know it is largely being left. Argonne's Aurora exascale machine was suppose to be Xeon Phi, but it has been postponed till 2021 and will likely use some other tech. Also look at the top 500 list from late 2017. Trinity the NNSA computer at #7 is Phi based but only gets about 50% of theoretical peak.

Phi is dead. The next NERSC computer is GPUs. Not sure what Argonne is doing but there’s no reason to think it won’t be GPUs. The only reason Phi/KNL made sense was because it seemed like a conservative choice when GPUs were more exotic, which may have been okay if Intel didn’t have the crazy yield problems they had. FPGAs don’t make sense because the conservative choice at this point is GPU. I don’t think any of the leading compute facilities have the stomach for a new technology like this, especially from intel.

Cmon it wasn't just yield problems. Premise that you can just recompile CPU code and it would run quickly on Phi was false.

It's a pity. Intel does have a compiler that works great for Xeon Phi: ISPC. Alas, it seems Intel was never serious about ISPC.

> The next NERSC computer is GPUs.

Got a source on this? I've not seen an official mention of what sort of architecture NERSC-9 will be.

> Not sure what Argonne is doing but there’s no reason to think it won’t be GPUs.

It will be a future Intel processor [1].

[1] https://www.hpcwire.com/2017/09/27/us-coalesces-plans-first-...

Nothing I can link to, but that information has been shared to DOE labs and projects relying on large NERSC allocations.

My personal tinfoil hat take is that Xeon Phi was made to make China waste top dollar on their supercomputers going with a less useful accelerator made by a US company.

By wasting millions of dollar and literally gave the Phi for free to China, which is part of the Intel CPU deal?

The answer is rather simple. Xeon Phi wasn't as good as the GPU counterpart.

Once China figured that out, the way they'd implement not falling for the same trick twice is simply never using US tech again. Which would limit other opportunities.

It's also at least plausible that they'd probably have people trained to think like Americans who might think of the same thing in advance.

Not if you believe Tom Forsyth

http://tomforsyth1000.github.io/blog.wiki.html#%5B%5BWhy%20d...

Yes US government has forbidden the export of Xeon and Xeon Phi to China's supercomputing centers. It prompted the construction of Sunway TaihuLight, which uses Chinese own CPUs.