This is not surprising - this is trade secret information as it directly translates to profit margin for the process. AFAIK nobody publishes process yield information other than vague handwavy percentages.

You should also expect percent yields of most processes these days to be pretty poor (numerically): each step brings its percent breakage along, so at 100+ steps for these current processes, you're losing a significant fraction of chips. (Even if all of your steps yield 99%, you're down to 36.6% yield after 100 steps, so it's really important to reduce the number of steps as well as their complexity.)

For a process to be profitable it doesn't need to have a perfect, or even "good" yield though (and so-called "perfect wafers" have been vanishingly rare since about the 14nm process step). I've read documentation about very old processes with yields of 60% that were considered "good" at the time, so 10% might not be a terrible overall yield at this process node (e.g. if we take our 36.6% yield example above, 10% total yield would be of 27% of theoretical - certainly room for improvement, but better than many pharmaceutical processes).

This underlines the importance for the switch to EUV - a dozen or more DUV multi-patterning steps can be dropped down to a single EUV step, which eliminates losses along those multi-patterning steps.

10% most certainly is a terrible yield. If TSMC is kicking off volume production, then they have a mostly-SRAM test vehicle somewhere, probably 288Mb or larger, yielding at 65 pct or better on a consistent basis. A 10% wafer would be a financial disaster.

60% Chance Apple will have a new iPad Pro in WWDC using 7nm, and 90% Chance Apple will use 7nm in their next iPhone.

Whatever the yield is, it is good enough for ~200M iPhone next year and the cost is acceptable for close to 50 customers in the next few months. And assuming Apple is going to go 7nm ( I don't see why not ), this volume will likely be more than double Intel shipping their 10nm in the next 12 months.