Agreed. About the only number I'd expect from a foundry is a defect density per unit area, which can be used to derive a yield estimate. It's die-size and design-quality dependent, so the quoted D0 is going to be a best case.

10% most certainly is a terrible yield. If TSMC is kicking off volume production, then they have a mostly-SRAM test vehicle somewhere, probably 288Mb or larger, yielding at 65 pct or better on a consistent basis. A 10% wafer would be a financial disaster.