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Re:EUV Lithography Finally Ready for Chip Manufacturing by dogma1138 on Monday January 08, 2018 @10:20AM (#16097270)
As I said nothin actually goes down to 7nm but they use multiple patterning basically the exposure or lack there off can be much finer than the wavelength of the light because they expose it multiple times through slightly different patterning.

Also ICs are made hang both subtractive and additive processes basically a series of exposures etches and depositions which at the end create the final product.

To put it simply if you have a 5mm mill you can still make a <5 mm feature by milling around say a 1mm square.

Re:EUV Lithography Finally Ready for Chip Manufacturing by contrarian_ on Monday January 08, 2018 @12:41PM (#16098364)
ELI5 why is the multiple patterning not additive in the same way as interference?
Re:EUV Lithography Finally Ready for Chip Manufacturing by dogma1138 on Monday January 08, 2018 @01:31PM (#16098685)
Forget the patterning and interference for a second.

The process isn’t a one off resist mask and etches you have a series of expose, etch and disposition passes over the material.

The actual feature size can be made much smaller because it can be the product of multiple exposures, etches and depositions.

So let’s say that the smallest feature size you have from a single mask is 200nm by using multiple masks and exposure you basically can build small features which are defined by the overlapping lit or shadow areas of the mask.

These features can also be ethched in a controlled manner to create even finer feature size.

To simplify it even further take make a shadow of an open palm with fingers fully extended so the gap between the fingers is the largest as you can make it and make an outline of the lit areas, now shift your hand slightly to the left or the right and make an outline of the shadowed area and subtract that from the previous outline it's now smaller without you having to change the size of your pattern or the wavelength of the light.

Re:EUV Lithography Finally Ready for Chip Manufacturing by posterboy on Monday January 08, 2018 @01:28PM (#16098677)
I have no idea really, but the above explanation implies reminds me on the double slit experiments. Also, inference is additive in the amplitude, but phase shifts much smaller than the wavelengths are used in interferometers to measure layer depths.

https://en.wikipedia.org/wiki/Double-slit_experiment

https://en.wikipedia.org/wiki/List_of_types_of_interferomete...

Re:EUV Lithography Finally Ready for Chip Manufacturing by dogma1138 on Monday January 08, 2018 @02:47PM (#16099653)
I believe it’s mostly single slit and diffraction, light can pass through holes smaller than its wavelength but even that isn’t needed just yet, nanophotonics will be the next step tho.

http://web.eecs.utk.edu/~jaynewu/Teaching/resolution.pdf

Re:EUV Lithography Finally Ready for Chip Manufacturing by rmu09 on Monday January 08, 2018 @02:36PM (#16099520)
The pattern still is constrained by the wavelength.

What is not constrained by wavelength is deposition and etching of layers, that could be (in theory at least) as thin as you like down to a monolayer.

With multipatterning you can place such small features, but the layout still is constrained by the wavelength.

Re:EUV Lithography Finally Ready for Chip Manufacturing by QAPereo on Monday January 08, 2018 @01:09PM (#16098552)
You’re not taking the resist mask into account, or multiple passes. https://en.m.wikipedia.org/wiki/Multiple_patterning

Not sure how to ELI5 it though...