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Re:Mill CPU Inter-Process Communication by PhilWright on Sunday October 08, 2017 @07:14PM (#15430562)
The Mill design is fascinating because it is genuinely very different to anything else. But it seems that the entire team might die from old age before they actually have any working silicon produced. Which would be a shame.
Re:Mill CPU Inter-Process Communication by thatswrong0 on Sunday October 08, 2017 @08:53PM (#15430894)
Innovative CPU architectures and popular fantasy novel series both..
Re:Mill CPU Inter-Process Communication by baking on Sunday October 08, 2017 @09:05PM (#15430945)
While I get the sense that this is Ivan's "baby" I'm pretty sure that he hasn't held anything back from the rest of the team and that they could carry on without him. Although his mind is as sharp as ever and his hair is fabulous so I'm not really worried about his health either.
Re:Mill CPU Inter-Process Communication by microcolonel on Sunday October 08, 2017 @08:57PM (#15430914)
Also, a popular computing textbook series.
Re:Mill CPU Inter-Process Communication by monk_e_boy on Sunday October 08, 2017 @07:18PM (#15430575)
Yeah, I'd love to see some more money or resources poured into this.
Re:Mill CPU Inter-Process Communication by igodard on Tuesday October 10, 2017 @04:04PM (#15444921)
So would we. See millcomputing.com -> About -> Invest in Us.
Re:Mill CPU Inter-Process Communication by CyberDildonics on Sunday October 08, 2017 @07:52PM (#15430673)
They aren't trying to produce silicon, they are trying to produce patents.
Re:Mill CPU Inter-Process Communication by microcolonel on Sunday October 08, 2017 @08:15PM (#15430745)
No, they are trying to produce silicon. This is their explicit goal. They're just recently caught up in filing a lot of patents because of changes to patent law.
Re:Mill CPU Inter-Process Communication by racer-v on Sunday October 08, 2017 @09:57PM (#15431129)
The goal of their first funding round was to create a patent portfolio; the second is earmarked for an FPGA implementation. Hard to do it the other way around, although to be honest FPGA dev kits are so cheap these days I don't know why this requires a funding round.
Re:Mill CPU Inter-Process Communication by jesstaa on Sunday October 08, 2017 @11:17PM (#15431368)
My understanding is that the cost of the FPGA implementation is about the cost of modifying the tooling that produces a Mill family member from a spec to produce Verilog as described in the 'Specification' talk https://millcomputing.com/docs/specification/
Re:Mill CPU Inter-Process Communication by jacquesm on Monday October 09, 2017 @05:53AM (#15432566)
Depends on the size of the chip you are trying to model, once your chip exceeds a certain level of complexity FPGA modeling can get expensive really quickly.

http://chipdesignmag.com/images/idesign/fpga/figure1.jpg

And such don't come cheap.

Re:Mill CPU Inter-Process Communication by racer-v on Wednesday October 11, 2017 @02:33AM (#15447693)
I suppose at $10K each, buying enough Altera Stratix 10 boards for the team could start to add up.
Re:Mill CPU Inter-Process Communication by mda on Friday October 13, 2017 @09:21AM (#15465333)
I don't understand this either, they could cut some corners and implement most promising ideas early. I think they delved too deep and it became too complex and alien. I would be surprised if there will be an actual mill cpu as described in the talks. Maybe eventually something that incorporates some of the ideas will be built, but not the whole enchilada.