Mill CPU Inter-Process Communication

Re:Mill CPU Inter-Process Communication by racer-v on Sunday October 08, 2017 @09:57PM (#15431129)

The goal of their first funding round was to create a patent portfolio; the second is earmarked for an FPGA implementation. Hard to do it the other way around, although to be honest FPGA dev kits are so cheap these days I don't know why this requires a funding round.

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Re:Mill CPU Inter-Process Communication by jesstaa on Sunday October 08, 2017 @11:17PM (#15431368)

My understanding is that the cost of the FPGA implementation is about the cost of modifying the tooling that produces a Mill family member from a spec to produce Verilog as described in the 'Specification' talk https://millcomputing.com/docs/specification/

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Re:Mill CPU Inter-Process Communication by jacquesm on Monday October 09, 2017 @05:53AM (#15432566)

Depends on the size of the chip you are trying to model, once your chip exceeds a certain level of complexity FPGA modeling can get expensive really quickly.

http://chipdesignmag.com/images/idesign/fpga/figure1.jpg

And such don't come cheap.

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Re:Mill CPU Inter-Process Communication by racer-v on Wednesday October 11, 2017 @02:33AM (#15447693)

I suppose at $10K each, buying enough Altera Stratix 10 boards for the team could start to add up.

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