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A comment on VHDL or Verilog?. Parent comment

Re:VHDL or Verilog? by krapht on Monday May 01, 2017 @02:10PM (#14239948)
Was Gaisler the first to write about it? I actually first heard about it from Mike Treseler, who is mentioned in this Powerpoint (http://ens.ewi.tudelft.nl/Education/courses/et4351/structure...)
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Re:VHDL or Verilog? by rektide on Monday May 01, 2017 @04:41PM (#14241348)
Slide 22 of this powerponit, Mike explicitly calls it Gaisler's Method. The term he uses "Structured VHDL" comes next slide.
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